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| author | ian <ian@FreeBSD.org> | 2014-05-14 17:40:18 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2014-05-14 17:40:18 +0000 |
| commit | 3c9602820517b21689d8a6153fd6f7ea38c7a749 (patch) | |
| tree | 5a1c9e79488178b15f78d541f8a651be6ee21573 /sys/arm/include | |
| parent | 4ee6f0bd3bade07595ecc84f07aa45d765a3eae1 (diff) | |
| download | FreeBSD-src-3c9602820517b21689d8a6153fd6f7ea38c7a749.zip FreeBSD-src-3c9602820517b21689d8a6153fd6f7ea38c7a749.tar.gz | |
MFC r258359, r258742, r258845, r259936, r259640
Apply access flags for managed and unmanaged pages properly on ARMv6/v7
Set the PGA_WRITEABLE flag when the protections indicate write access, not
just when the current access is a write.
Enable missing Access Flag for secondary cores on ARMv6/v7
Add identification and necessary type checks for Krait CPU cores.
Diffstat (limited to 'sys/arm/include')
| -rw-r--r-- | sys/arm/include/armreg.h | 1 | ||||
| -rw-r--r-- | sys/arm/include/cpuconf.h | 5 | ||||
| -rw-r--r-- | sys/arm/include/cpufunc.h | 4 | ||||
| -rw-r--r-- | sys/arm/include/intr.h | 2 | ||||
| -rw-r--r-- | sys/arm/include/md_var.h | 1 |
5 files changed, 9 insertions, 4 deletions
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 35d2e9f..9397678 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -157,6 +157,7 @@ #define CPU_ID_CORTEXA15 0x410fc0f0 #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 +#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ #define CPU_ID_TI925T 0x54029250 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ #define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h index 986633b..0c2faa3 100644 --- a/sys/arm/include/cpuconf.h +++ b/sys/arm/include/cpuconf.h @@ -66,6 +66,7 @@ defined(CPU_FA626TE) + \ defined(CPU_XSCALE_IXP425)) + \ defined(CPU_CORTEXA) + \ + defined(CPU_KRAIT) + \ defined(CPU_MV_PJ4B) /* @@ -97,7 +98,7 @@ #endif #endif -#if defined(CPU_CORTEXA) +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #define ARM_ARCH_7A 1 #else #define ARM_ARCH_7A 0 @@ -156,7 +157,7 @@ #define ARM_MMU_V6 0 #endif -#if defined(CPU_CORTEXA) +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #define ARM_MMU_V7 1 #else #define ARM_MMU_V7 0 diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index d3e9ebe..0b53906 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -188,7 +188,7 @@ extern u_int cputype; #else void tlb_broadcast(int); -#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) #define TLB_BROADCAST /* No need to explicitely send an IPI */ #else #define TLB_BROADCAST tlb_broadcast(7) @@ -463,7 +463,7 @@ void sheeva_l2cache_wbinv_all (void); #endif #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \ - defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) + defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) void arm11_setttb (u_int); void arm11_sleep (int); diff --git a/sys/arm/include/intr.h b/sys/arm/include/intr.h index 93a204c..a3bc837 100644 --- a/sys/arm/include/intr.h +++ b/sys/arm/include/intr.h @@ -52,6 +52,8 @@ #define NIRQ 64 #elif defined(CPU_CORTEXA) #define NIRQ 160 +#elif defined(CPU_KRAIT) +#define NIRQ 288 #elif defined(CPU_ARM1136) || defined(CPU_ARM1176) #define NIRQ 128 #elif defined(SOC_MV_ARMADAXP) diff --git a/sys/arm/include/md_var.h b/sys/arm/include/md_var.h index efb973d..ef202f5 100644 --- a/sys/arm/include/md_var.h +++ b/sys/arm/include/md_var.h @@ -63,6 +63,7 @@ enum cpu_class { CPU_CLASS_ARM10E, CPU_CLASS_ARM10EJ, CPU_CLASS_CORTEXA, + CPU_CLASS_KRAIT, CPU_CLASS_SA1, CPU_CLASS_XSCALE, CPU_CLASS_ARM11J, |
