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| author | ian <ian@FreeBSD.org> | 2014-05-14 16:32:27 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2014-05-14 16:32:27 +0000 |
| commit | 13afdc288fd9e982249ab19116c195578ff90fa1 (patch) | |
| tree | a7f1a8aa7e8f1518d3c62bbfe659e0a16f4cb25a /sys/arm/include | |
| parent | bb1ce472d77ae881d92bd8dbbc84cf2c24edb5e4 (diff) | |
| download | FreeBSD-src-13afdc288fd9e982249ab19116c195578ff90fa1.zip FreeBSD-src-13afdc288fd9e982249ab19116c195578ff90fa1.tar.gz | |
MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,
r257282, r257332
Wait for DesignWare UART transfers completion before accessing line control
Enable UART busy detection handling for Armada XP - based board
Enable SATA interface on Armada XP
Run mvs SATA driver on Armada XP instead of old mv_sata
Retire arm_remap_nocache() and the data and constants associated with it.
Remove hard-coded mappings related to Armada XP support
Fix-up DTB for Armada XP registers' base according to the actual settings
Change Armada XP kernel load address to the u-boot's end address
Remove not working and deprecated PJ4Bv6 support
Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU
Add missing ARMv6 CPU functions to ARM Makefile
Diffstat (limited to 'sys/arm/include')
| -rw-r--r-- | sys/arm/include/armreg.h | 4 | ||||
| -rw-r--r-- | sys/arm/include/cpufunc.h | 11 |
2 files changed, 1 insertions, 14 deletions
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index d47f743..35d2e9f 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -172,14 +172,10 @@ #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ #endif -#define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */ #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ -#define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */ #define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ /* Marvell's CPUIDs with ARM ID in implementor field */ -#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ -#define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */ #define CPU_ID_FA526 0x66015260 #define CPU_ID_FA626TE 0x66056260 diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index 07c8258..d3e9ebe 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -188,7 +188,7 @@ extern u_int cputype; #else void tlb_broadcast(int); -#ifdef CPU_CORTEXA +#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) #define TLB_BROADCAST /* No need to explicitely send an IPI */ #else #define TLB_BROADCAST tlb_broadcast(7) @@ -482,14 +482,6 @@ void arm11_drain_writebuf (void); void pj4b_setttb (u_int); -void pj4b_icache_sync_range (vm_offset_t, vm_size_t); - -void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t); -void pj4b_dcache_inv_range (vm_offset_t, vm_size_t); -void pj4b_dcache_wb_range (vm_offset_t, vm_size_t); - -void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t); - void pj4b_drain_readbuf (void); void pj4b_flush_brnchtgt_all (void); void pj4b_flush_brnchtgt_va (u_int); @@ -523,7 +515,6 @@ void armv7_drain_writebuf (void); void armv7_sev (void); u_int armv7_auxctrl (u_int, u_int); void pj4bv7_setup (char *string); -void pj4bv6_setup (char *string); void pj4b_config (void); int get_core_id (void); |
