MFC 263910, 263913, 263914, 263933, 263934, 263935, 263936, 263981, 263982,

  Add more flags for the fpexc register from the ARM1176JZF-S Manual

  Initialise fpscr to a sane value when we create the pcb. This sets NaNs to
  be the default NaN and for denormalised numbers to be flushed to zero.

  VFP fixes/cleanups for ARM11:
   * Save the required VFP registers on context switch. If the exception bit
     is set we need to save and restore the FPINST register, and if the fp2v
     bit is also set we need to save and restore FPINST2.
   * Move saving and restoring the floating point control registers to C.
   * Clear the fpexc exception and fp2v flags on a floating-point exception.
   * Signal a SIGFPE if the fpexc exception flag is set on an undefined
     instruction. This is how the ARM core signals to software there is a
     floating-point exception.

  Add Cortex-A15 cpu id revisions.

  Exynos/Arndale...
  - Merge SoC-common parts
  - Enable iicbus device
  - Directly call kmem_alloc_contig to allocate framebuffer memory
    and pass VM_MEMATTR_UNCACHEABLE (no-cache, no-buffer).
    This fixes screen refreshing problem when data is updated too slowly.
  - Add support for keyboard used in Samsung Chromebook (ARM machine)
    Support covers device drivers for:
    - Interrupt Combiner
    - gpio/pad, External Interrupts Controller (pad)
    - I2C Interface
    - Chrome Embedded Controller
    - Chrome Keyboard
  - Use new gpio dev class in EHCI driver
  - Expand device tree information
  - Release i2c bus on detach.

3 files changed, 12 insertions, 1 deletions

diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h
index 8e02621..3a6d0c0 100644
--- a/sys/arm/include/armreg.h
+++ b/sys/arm/include/armreg.h
@@ -122,7 +122,10 @@
 #define CPU_ID_CORTEXA9R1	0x411fc090
 #define CPU_ID_CORTEXA9R2	0x412fc090
 #define CPU_ID_CORTEXA9R3	0x413fc090
-#define CPU_ID_CORTEXA15	0x410fc0f0
+#define CPU_ID_CORTEXA15R0	0x410fc0f0
+#define CPU_ID_CORTEXA15R1	0x411fc0f0
+#define CPU_ID_CORTEXA15R2	0x412fc0f0
+#define CPU_ID_CORTEXA15R3	0x413fc0f0
 #define	CPU_ID_KRAIT		0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */
 #define	CPU_ID_TI925T		0x54029250
 #define CPU_ID_MV88FR131	0x56251310 /* Marvell Feroceon 88FR131 Core */
diff --git a/sys/arm/include/fp.h b/sys/arm/include/fp.h
index b7a1b8a..8817d84 100644
--- a/sys/arm/include/fp.h
+++ b/sys/arm/include/fp.h
@@ -69,6 +69,9 @@ typedef struct fp_extended_precision fp_reg_t;
 struct vfp_state {
 	u_int64_t reg[32];
 	u_int32_t fpscr;
+	u_int32_t fpexec;
+	u_int32_t fpinst;
+	u_int32_t fpinst2;
 };
 
 /*
diff --git a/sys/arm/include/vfp.h b/sys/arm/include/vfp.h
index befba18..62345ce 100644
--- a/sys/arm/include/vfp.h
+++ b/sys/arm/include/vfp.h
@@ -92,6 +92,11 @@
 /* VFPEXC */
 #define	VFPEXC_EX 		(0x80000000)	/* exception v1 v2 */
 #define	VFPEXC_EN		(0x40000000)	/* vfp enable */
+#define	VFPEXC_FP2V		(0x10000000)	/* FPINST2 valid */
+#define	VFPEXC_INV		(0x00000080)	/* Input exception */
+#define	VFPEXC_UFC		(0x00000008)	/* Underflow exception */
+#define	VFPEXC_OFC		(0x00000004)	/* Overflow exception */
+#define	VFPEXC_IOC		(0x00000001)	/* Invlaid operation */
 
 /* version 3 registers */
 /* VMVFR0 */