MFC 265861, 265870:

  Make the hardware memory and instruction barrier functions work on armv4
  and armv5 as well.

  Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

2 files changed, 5 insertions, 3 deletions

diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h
index 4ac5a3f..f07fcef 100644
--- a/sys/arm/include/atomic.h
+++ b/sys/arm/include/atomic.h
@@ -58,9 +58,9 @@
 #define dsb()  __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
 #define dmb()  __asm __volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory")
 #else
-#define isb()
-#define dsb()
-#define dmb()
+#define isb()  __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory")
+#define dsb()  __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
+#define dmb()  dsb()
 #endif
 
 #define mb()   dmb()
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index c2a96a8..16887b0 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -151,6 +151,7 @@ struct cpu_functions {
 	void	(*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
 	void	(*cf_l2cache_inv_range)	  (vm_offset_t, vm_size_t);
 	void	(*cf_l2cache_wb_range)	  (vm_offset_t, vm_size_t);
+	void	(*cf_l2cache_drain_writebuf)	  (void);
 
 	/* Other functions */
 
@@ -252,6 +253,7 @@ void tlb_broadcast(int);
 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
+#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
 
 #define	cpu_flush_prefetchbuf()	cpufuncs.cf_flush_prefetchbuf()
 #define	cpu_drain_writebuf()	cpufuncs.cf_drain_writebuf()