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| author | ian <ian@FreeBSD.org> | 2015-05-23 22:48:54 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2015-05-23 22:48:54 +0000 |
| commit | 68a3dfa74060bcbbac11eaa545bab9c26c9f879e (patch) | |
| tree | 62fb5737b6b5dbcb35ff2fdaebc2788e1bf44778 /sys/arm/include | |
| parent | 011666b0a8c74e747a5483f15fb01e9ac7dac93c (diff) | |
| download | FreeBSD-src-68a3dfa74060bcbbac11eaa545bab9c26c9f879e.zip FreeBSD-src-68a3dfa74060bcbbac11eaa545bab9c26c9f879e.tar.gz | |
MFC r278518: Resolve cache line size from CP15 instead of hard-coded 32.
Diffstat (limited to 'sys/arm/include')
| -rw-r--r-- | sys/arm/include/armreg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 3788d0d..c071989 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -318,6 +318,9 @@ #define CPU_CT_S (1U << 24) /* split cache */ #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ #define CPU_CT_FORMAT(x) ((x) >> 29) +/* Cache type register definitions for ARM v7 */ +#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */ +#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */ #define CPU_CT_CTYPE_WT 0 /* write-through */ #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ |
