MFC 263631, 263637, 263664, 263676, 263679, 263698, 263711,

  Implement __flt_rounds for ARMv6 hard-float. The fpscr register stores the
  current rounding mode used by the VFP unit.

  Simplify how we build MACHINE_ARCH. There are 3 options that may be set
  however only arm, armeb, armv6, and soon armv6hf will be used.

  Add the llvm/clang patch for r263619.

  Reorder the pmap macros so "ARM_MMU_V6 + ARM_MMU_V7" is first. As they are
  identical this allows us to build for both v6 and v7 together.

  Add code for enabling second CPU core for A20 SoC.
  Enable SMP on Cubieboard2.

  Switch to freebsd.org emal address in copyright.

2 files changed, 57 insertions, 50 deletions

diff --git a/sys/arm/include/param.h b/sys/arm/include/param.h
index ab5b406..d28a2b3 100644
--- a/sys/arm/include/param.h
+++ b/sys/arm/include/param.h
@@ -52,23 +52,29 @@
 
 #define __PCI_REROUTE_INTERRUPT
 
-#ifndef MACHINE
-#define	MACHINE		"arm"
-#endif
-#ifndef MACHINE_ARCH
 #if defined(__FreeBSD_ARCH_armv6__) || (defined(__ARM_ARCH) && __ARM_ARCH >= 6)
-#ifdef __ARMEB__
-#define	MACHINE_ARCH	"armv6eb"
+#define	_V6_SUFFIX "v6"
 #else
-#define	MACHINE_ARCH	"armv6"
+#define	_V6_SUFFIX ""
 #endif
+
+#ifdef __ARM_PCS_VFP
+#define	_HF_SUFFIX "hf"
 #else
+#define	_HF_SUFFIX ""
+#endif
+
 #ifdef __ARMEB__
-#define	MACHINE_ARCH	"armeb"
+#define	_EB_SUFFIX "eb"
 #else
-#define	MACHINE_ARCH	"arm"
+#define	_EB_SUFFIX ""
 #endif
+
+#ifndef MACHINE
+#define	MACHINE		"arm"
 #endif
+#ifndef MACHINE_ARCH
+#define	MACHINE_ARCH	"arm" _V6_SUFFIX _HF_SUFFIX _EB_SUFFIX
 #endif
 
 #if defined(SMP) || defined(KLD_MODULE)
diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h
index 00080b9..70c337a 100644
--- a/sys/arm/include/pmap.h
+++ b/sys/arm/include/pmap.h
@@ -341,47 +341,7 @@ extern int pmap_needs_pte_sync;
 #define	L2_AP(x)	(L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
 #endif
 
-#if ARM_NMMUS > 1
-/* More than one MMU class configured; use variables. */
-#define	L2_S_PROT_U		pte_l2_s_prot_u
-#define	L2_S_PROT_W		pte_l2_s_prot_w
-#define	L2_S_PROT_MASK		pte_l2_s_prot_mask
-
-#define	L1_S_CACHE_MASK		pte_l1_s_cache_mask
-#define	L2_L_CACHE_MASK		pte_l2_l_cache_mask
-#define	L2_S_CACHE_MASK		pte_l2_s_cache_mask
-
-#define	L1_S_PROTO		pte_l1_s_proto
-#define	L1_C_PROTO		pte_l1_c_proto
-#define	L2_S_PROTO		pte_l2_s_proto
-
-#elif ARM_MMU_GENERIC != 0
-#define	L2_S_PROT_U		L2_S_PROT_U_generic
-#define	L2_S_PROT_W		L2_S_PROT_W_generic
-#define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
-
-#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
-#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
-#define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
-
-#define	L1_S_PROTO		L1_S_PROTO_generic
-#define	L1_C_PROTO		L1_C_PROTO_generic
-#define	L2_S_PROTO		L2_S_PROTO_generic
-
-#elif ARM_MMU_XSCALE == 1
-#define	L2_S_PROT_U		L2_S_PROT_U_xscale
-#define	L2_S_PROT_W		L2_S_PROT_W_xscale
-#define	L2_S_PROT_MASK		L2_S_PROT_MASK_xscale
-
-#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_xscale
-#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_xscale
-#define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_xscale
-
-#define	L1_S_PROTO		L1_S_PROTO_xscale
-#define	L1_C_PROTO		L1_C_PROTO_xscale
-#define	L2_S_PROTO		L2_S_PROTO_xscale
-
-#elif (ARM_MMU_V6 + ARM_MMU_V7) != 0
+#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
 /*
  * AP[2:1] access permissions model:
  *
@@ -486,6 +446,47 @@ extern int pmap_needs_pte_sync;
 #define ARM_L2S_NRML_IWB_OWB	(L2_C|L2_B|L2_SHARED)
 #define ARM_L2S_NRML_IWBA_OWBA	(L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
 #endif /* SMP */
+
+#elif ARM_NMMUS > 1
+/* More than one MMU class configured; use variables. */
+#define	L2_S_PROT_U		pte_l2_s_prot_u
+#define	L2_S_PROT_W		pte_l2_s_prot_w
+#define	L2_S_PROT_MASK		pte_l2_s_prot_mask
+
+#define	L1_S_CACHE_MASK		pte_l1_s_cache_mask
+#define	L2_L_CACHE_MASK		pte_l2_l_cache_mask
+#define	L2_S_CACHE_MASK		pte_l2_s_cache_mask
+
+#define	L1_S_PROTO		pte_l1_s_proto
+#define	L1_C_PROTO		pte_l1_c_proto
+#define	L2_S_PROTO		pte_l2_s_proto
+
+#elif ARM_MMU_GENERIC != 0
+#define	L2_S_PROT_U		L2_S_PROT_U_generic
+#define	L2_S_PROT_W		L2_S_PROT_W_generic
+#define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
+
+#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
+#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
+#define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
+
+#define	L1_S_PROTO		L1_S_PROTO_generic
+#define	L1_C_PROTO		L1_C_PROTO_generic
+#define	L2_S_PROTO		L2_S_PROTO_generic
+
+#elif ARM_MMU_XSCALE == 1
+#define	L2_S_PROT_U		L2_S_PROT_U_xscale
+#define	L2_S_PROT_W		L2_S_PROT_W_xscale
+#define	L2_S_PROT_MASK		L2_S_PROT_MASK_xscale
+
+#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_xscale
+#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_xscale
+#define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_xscale
+
+#define	L1_S_PROTO		L1_S_PROTO_xscale
+#define	L1_C_PROTO		L1_C_PROTO_xscale
+#define	L2_S_PROTO		L2_S_PROTO_xscale
+
 #endif /* ARM_NMMUS > 1 */
 
 #if defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A