MFC r261414, r261415, r261417, r261418, r261419

  Don't call device_set_ivars() for the mmchs

  Change the way pcpu and curthread are stored per-core

  Invalidate cachelines for bounce pages on PREREAD too, there may still be
  stale entries from a previous transfer.

  Only use the CPU ID register if SMP is defined. Some non-MPCore armv6 cpu,
  such as the one found in the RPi, don't have it, and just hang when we try
  to access it.

1 files changed, 24 insertions, 7 deletions

diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h
index 6e0eb06..1771a8e 100644
--- a/sys/arm/include/pcpu.h
+++ b/sys/arm/include/pcpu.h
@@ -62,22 +62,36 @@ struct pcpu;
 extern struct pcpu *pcpup;
 #if ARM_ARCH_6 || ARM_ARCH_7A
 /* or ARM_TP_ADDRESS 	mark REMOVE ME NOTE */
-static inline struct pcpu *
-get_pcpu(void)
+
+#define CPU_MASK (0xf)
+
+#ifndef SMP
+#define get_pcpu() (pcpup)
+#else
+#define get_pcpu() __extension__ ({			  		\
+    	int id;								\
+        __asm __volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (id));	\
+    	(pcpup + (id & CPU_MASK));					\
+    })
+#endif
+	
+static inline struct thread *
+get_curthread(void)
 {
-	void *pcpu;
+	void *ret;
 
-	__asm __volatile("mrc p15, 0, %0, c13, c0, 4" : "=r" (pcpu));
-	return (pcpu);
+	__asm __volatile("mrc p15, 0, %0, c13, c0, 4" : "=r" (ret));
+	return (ret);
 }
 
 static inline void
-set_pcpu(void *pcpu)
+set_curthread(struct thread *td)
 {
 
-	__asm __volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (pcpu));
+	__asm __volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (td));
 }
 
+
 static inline void *
 get_tls(void)
 {
@@ -93,6 +107,9 @@ set_tls(void *tls)
 
 	__asm __volatile("mcr p15, 0, %0, c13, c0, 3" : : "r" (tls));
 }
+
+#define curthread get_curthread()
+
 #else
 #define get_pcpu()	pcpup
 #endif