MFC 265440, 265441, 265444, 265445, 265446, 265447:

  Move the pl310.enabled tunable to hw.pl310.enabled.  Clean up a few minor
  style(9) nits.  Use DEVMETHOD_END.

  Break out the code that figures out the L2 cache geometry to its own
  routine, so that it can be called from multiple places in upcoming changes.

  Call platform_pl310_init() before enabling the controller, and handle the
  case where the controller is already enabled.

  Add defines for the bits in the PL310 debug control register.

  Add a public routine to set the L2 cache ram latencies.  This can be
  called by platform init routines to fine-tune cache performance.

  Enable PL310 power-saving modes and tune the cache ram latencies for imx6.

1 files changed, 13 insertions, 0 deletions

diff --git a/sys/arm/freescale/imx/imx6_pl310.c b/sys/arm/freescale/imx/imx6_pl310.c
index a4e383e..9e0427f 100644
--- a/sys/arm/freescale/imx/imx6_pl310.c
+++ b/sys/arm/freescale/imx/imx6_pl310.c
@@ -44,6 +44,19 @@ __FBSDID("$FreeBSD$");
 void
 platform_pl310_init(struct pl310_softc *sc)
 {
+	uint32_t reg;
+
+	/*
+	 * Enable power saving modes:
+	 *  - Dynamic Gating stops the clock when the controller is idle.
+	 *  - Standby stops the clock when the cores are in WFI mode.
+	 */
+	reg = pl310_read4(sc, PL310_POWER_CTRL);
+	reg |= POWER_CTRL_ENABLE_GATING | POWER_CTRL_ENABLE_STANDBY;
+	pl310_write4(sc, PL310_POWER_CTRL, reg);
+
+	pl310_set_ram_latency(sc, PL310_TAG_RAM_CTRL,  4, 2, 3);
+	pl310_set_ram_latency(sc, PL310_DATA_RAM_CTRL, 4, 2, 3);
 }
 
 void