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| author | imp <imp@FreeBSD.org> | 2014-08-14 23:17:33 +0000 |
|---|---|---|
| committer | imp <imp@FreeBSD.org> | 2014-08-14 23:17:33 +0000 |
| commit | 6a0dd771d986a0c83351a68f884ef725d9853ccb (patch) | |
| tree | 988c86974a19db4568a1d6f5c96599b827692842 /sys/arm/at91 | |
| parent | 5763b41c84c2c0ced743d5c4264a47a0df1e230a (diff) | |
| download | FreeBSD-src-6a0dd771d986a0c83351a68f884ef725d9853ccb.zip FreeBSD-src-6a0dd771d986a0c83351a68f884ef725d9853ccb.tar.gz | |
Print the symbolic bit names for the status when we get a timeout.
Diffstat (limited to 'sys/arm/at91')
| -rw-r--r-- | sys/arm/at91/at91_mci.c | 4 | ||||
| -rw-r--r-- | sys/arm/at91/at91_mcireg.h | 24 |
2 files changed, 26 insertions, 2 deletions
diff --git a/sys/arm/at91/at91_mci.c b/sys/arm/at91/at91_mci.c index 5d58228..b9bc047 100644 --- a/sys/arm/at91/at91_mci.c +++ b/sys/arm/at91/at91_mci.c @@ -1210,8 +1210,8 @@ at91_mci_intr(void *arg) */ if (cmd->opcode != 8) { device_printf(sc->dev, - "IO error; status MCI_SR = 0x%x cmd opcode = %d%s\n", - sr, cmd->opcode, + "IO error; status MCI_SR = 0x%b cmd opcode = %d%s\n", + sr, MCI_SR_BITSTRING, cmd->opcode, (cmd->opcode != 12) ? "" : (sc->flags & CMD_MULTIREAD) ? " after read" : " after write"); at91_mci_reset(sc); diff --git a/sys/arm/at91/at91_mcireg.h b/sys/arm/at91/at91_mcireg.h index 87b08ab..1831c0d 100644 --- a/sys/arm/at91/at91_mcireg.h +++ b/sys/arm/at91/at91_mcireg.h @@ -118,6 +118,30 @@ #define MCI_SR_OVRE (0x1u << 30) /* (MCI) Overrun flag */ #define MCI_SR_UNRE (0x1u << 31) /* (MCI) Underrun flag */ +/* TXRDY,DTIP,ENDTX,TXBUFE,RTOE */ + +#define MCI_SR_BITSTRING \ + "\020" \ + "\001CMDRDY" \ + "\002RXRDY" \ + "\003TXRDY" \ + "\004BLKE" \ + "\005DTIP" \ + "\006NOTBUSY" \ + "\007ENDRX" \ + "\010ENDTX" \ + "\017RXBUFF" \ + "\020TXBUFE" \ + "\021RINDE" \ + "\022RDIRE" \ + "\023RCRCE" \ + "\024RENDE" \ + "\025RTOE" \ + "\026DCRCE" \ + "\027DTOE" \ + "\037OVRE" \ + "\040UNRE" + /* -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- */ /* -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- */ /* -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- */ |
