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author | Renato Botelho <renato@netgate.com> | 2016-05-09 17:39:43 -0300 |
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committer | Renato Botelho <renato@netgate.com> | 2016-05-09 17:39:43 -0300 |
commit | 20ab79d9560e0036f834689a67c3035c18e3eb43 (patch) | |
tree | ee1296285669938e8ca9f3215719c5e461aab23b /sys/arm/at91 | |
parent | 394097451eda898069e18b8dc01759b5ec2d19ff (diff) | |
parent | 751248c9f444f5d00818a67a793dc0319749f236 (diff) | |
download | FreeBSD-src-20ab79d9560e0036f834689a67c3035c18e3eb43.zip FreeBSD-src-20ab79d9560e0036f834689a67c3035c18e3eb43.tar.gz |
Merge remote-tracking branch 'origin/master' into devel-11
Diffstat (limited to 'sys/arm/at91')
-rw-r--r-- | sys/arm/at91/at91_cfata.c | 2 | ||||
-rw-r--r-- | sys/arm/at91/at91_machdep.c | 2 | ||||
-rw-r--r-- | sys/arm/at91/at91_mci.c | 4 | ||||
-rw-r--r-- | sys/arm/at91/at91_reset.S | 2 | ||||
-rw-r--r-- | sys/arm/at91/at91reg.h | 4 | ||||
-rw-r--r-- | sys/arm/at91/at91sam9260.c | 2 | ||||
-rw-r--r-- | sys/arm/at91/if_ate.c | 12 | ||||
-rw-r--r-- | sys/arm/at91/if_atereg.h | 4 |
8 files changed, 16 insertions, 16 deletions
diff --git a/sys/arm/at91/at91_cfata.c b/sys/arm/at91/at91_cfata.c index 37ce434..d4848ff 100644 --- a/sys/arm/at91/at91_cfata.c +++ b/sys/arm/at91/at91_cfata.c @@ -26,7 +26,7 @@ * common memory mode. Interrupts are driven by polling. The driver * implements an ATA bridge and attached ATA channel driver on top * of it. - * NOTE WELL: this driver uses polling mode. To achive an acceptable + * NOTE WELL: this driver uses polling mode. To achieve an acceptable * operating speed you will probably want to use HZ=2000 in kernel * config. */ diff --git a/sys/arm/at91/at91_machdep.c b/sys/arm/at91/at91_machdep.c index b6ff9ca..6be7f72 100644 --- a/sys/arm/at91/at91_machdep.c +++ b/sys/arm/at91/at91_machdep.c @@ -36,7 +36,7 @@ * * machdep.c * - * Machine dependant functions for kernel setup + * Machine dependent functions for kernel setup * * This file needs a lot of work. * diff --git a/sys/arm/at91/at91_mci.c b/sys/arm/at91/at91_mci.c index cf884b9..bb5b7d5 100644 --- a/sys/arm/at91/at91_mci.c +++ b/sys/arm/at91/at91_mci.c @@ -92,7 +92,7 @@ __FBSDID("$FreeBSD$"); * speed is 25MHz and the next highest speed is 15MHz or less. This appears * to work on virtually all SD cards, since it is what this driver has been * doing prior to the introduction of this option, where the overclocking vs - * underclocking decision was automaticly "overclock". Modern SD cards can + * underclocking decision was automatically "overclock". Modern SD cards can * run at 45mhz/1-bit in standard mode (high speed mode enable commands not * sent) without problems. * @@ -212,7 +212,7 @@ at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t mem /* * If the hardware doesn't need byte-swapping, let bcopy() do the * work. Use bounce buffer even if we don't need byteswap, since - * buffer may straddle a page boundry, and we don't handle + * buffer may straddle a page boundary, and we don't handle * multi-segment transfers in hardware. Seen from 'bsdlabel -w' which * uses raw geom access to the volume. Greg Ansley (gja (at) * ansley.com) diff --git a/sys/arm/at91/at91_reset.S b/sys/arm/at91/at91_reset.S index 28703cc..36d72e4 100644 --- a/sys/arm/at91/at91_reset.S +++ b/sys/arm/at91/at91_reset.S @@ -14,7 +14,7 @@ __FBSDID("$FreeBSD$"); /* * From AT91SAM9G20 Datasheet errata 44:3.5: * - * When User Reset occurs durring SDRAM read acces, eh SDRAM clock is turned + * When User Reset occurs during SDRAM read access, the SDRAM clock is turned * off while data are ready to be read on the data bus. The SDRAM maintains * the data until the clock restarts. * diff --git a/sys/arm/at91/at91reg.h b/sys/arm/at91/at91reg.h index e0aaa81..35e14f5 100644 --- a/sys/arm/at91/at91reg.h +++ b/sys/arm/at91/at91reg.h @@ -39,9 +39,9 @@ #define AT91_PA_BASE 0xf0000000 /* A few things that we count on being the same - * throught the whole family of SOCs */ + * throughout the whole family of SOCs */ -/* SYSC System Controler */ +/* SYSC System Controller */ /* System Registers */ #define AT91_SYS_BASE 0xffff000 #define AT91_SYS_SIZE 0x1000 diff --git a/sys/arm/at91/at91sam9260.c b/sys/arm/at91/at91sam9260.c index 5b0f537..4514d87 100644 --- a/sys/arm/at91/at91sam9260.c +++ b/sys/arm/at91/at91sam9260.c @@ -188,7 +188,7 @@ at91_clock_init(void) * PMC alogrithm choose the divisor that causes the input clock * to be near the optimal 2 MHz per datasheet. We know * we are going to be using this for the USB clock at 96 MHz. - * Causes no extra frequency deviation for all recomended crystal + * Causes no extra frequency deviation for all recommended crystal * values. See Note 1, table 40-16 SAM9260 doc. */ clk = at91_pmc_clock_ref("pllb"); diff --git a/sys/arm/at91/if_ate.c b/sys/arm/at91/if_ate.c index 082b24f..fdca46b 100644 --- a/sys/arm/at91/if_ate.c +++ b/sys/arm/at91/if_ate.c @@ -651,7 +651,7 @@ ate_activate(device_t dev) ate_getaddr, &sc->tx_desc_phys, 0) != 0) goto errout; - /* Initilize descriptors; mark all empty */ + /* Initialize descriptors; mark all empty */ for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { sc->tx_descs[i].addr =0; sc->tx_descs[i].status = ETHB_TX_USED; @@ -919,7 +919,7 @@ ate_intr(void *xsc) /* * Simulate SAM9 FIRST/LAST bits for RM9200. * RM9200 EMAC has only on Rx buffer per packet. - * But sometime we are handed a zero lenght packet. + * But sometime we are handed a zero length packet. */ if ((rxdhead->status & ETH_LEN_MASK) == 0) rxdhead->status = 0; /* Mark error */ @@ -980,7 +980,7 @@ ate_intr(void *xsc) do { /* Last buffer may just be 1-4 bytes of FCS so remain - * may be zero for last decriptor. */ + * may be zero for last descriptor. */ if (remain > 0) { /* Make sure we get the current bytes */ bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], @@ -989,7 +989,7 @@ ate_intr(void *xsc) count = MIN(remain, sc->rx_buf_size); /* XXX Performance robbing copy. Could - * recieve directly to mbufs if not an + * receive directly to mbufs if not an * RM9200. And even then we could likely * copy just the protocol headers. XXX */ m_append(mb, count, sc->rx_buf[sc->rxhead]); @@ -1468,7 +1468,7 @@ ate_miibus_readreg(device_t dev, int phy, int reg) int val; /* - * XXX if we implement agressive power savings, then we need + * XXX if we implement aggressive power savings, then we need * XXX to make sure that the clock to the emac is on here */ @@ -1488,7 +1488,7 @@ ate_miibus_writereg(device_t dev, int phy, int reg, int data) struct ate_softc *sc; /* - * XXX if we implement agressive power savings, then we need + * XXX if we implement aggressive power savings, then we need * XXX to make sure that the clock to the emac is on here */ diff --git a/sys/arm/at91/if_atereg.h b/sys/arm/at91/if_atereg.h index fc7e4de..c6cbbcf 100644 --- a/sys/arm/at91/if_atereg.h +++ b/sys/arm/at91/if_atereg.h @@ -28,7 +28,7 @@ #ifndef ARM_AT91_IF_ATEREG_H #define ARM_AT91_IF_ATEREG_H -/* deines begining ETHB_ are EMACB (newer SAM9 hardware) versions only */ +/* Defines beginning ETHB_ are EMACB (newer SAM9 hardware) versions only. */ #define ETH_CTL 0x00 /* EMAC Control Register */ #define ETH_CFG 0x04 /* EMAC Configuration Register */ @@ -191,7 +191,7 @@ typedef struct { #define ETH_MAC_LOCAL_3 (1U << 24) /* Packet matched addr 3 */ #define ETH_MAC_LOCAL_2 (1U << 25) /* Packet matched addr 2 */ #define ETH_MAC_LOCAL_1 (1U << 26) /* Packet matched addr 1 */ -#define ETH_MAC_UNK (1U << 27) /* Unkown source address RFU */ +#define ETH_MAC_UNK (1U << 27) /* Unknown source address RFU */ #define ETH_MAC_EXT (1U << 28) /* External Address */ #define ETH_MAC_UCAST (1U << 29) /* Unicast hash match */ #define ETH_MAC_MCAST (1U << 30) /* Multicast hash match */ |