MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,

    263030, 263033, 263034, 263056, 263057,

  Remove all the redundant external declarations of exception vectors and
  runtime setting of the pointers that's scattered around various places.

  Remove all traces of support for ARM chips prior to the arm9 series.

  Make the default exception handler vectors point to where I thought they
  were already pointing: the default handlers (not a panic that says there
  is no default handler).

  Eliminate irq_dispatch.S.  Move the data items it contained into
  arm/intr.c and the functionality it provided into arm/exception.S.

  Move the exception vector table (so-called "page0" data) into exception.S
  and eliminate vectors.S.

  Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
  using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.

  Arrange for arm fork_trampoline() to return to userland via the standard
  swi_exit code in exception.S instead of having its own inline expansion
  of the DO_AST and PULLFRAME macros.

  Now that the PUSHFRAME and PULLFRAME macros are used only in the swi
  entry/exit code, they don't need to be macros.  Except that didn't work
  and the whole change was reverted.

  Remove some unnecessary indirection and jump right to the handler functions.

  Use panic rather than printf to "handle" an arm26 address exception
  (should never happen on arm32).

  Remove the unreferenced DATA() macro.

  Remove #include <machine/asmacros.h> from files that don't need it.

21 files changed, 388 insertions, 2715 deletions

diff --git a/sys/arm/arm/copystr.S b/sys/arm/arm/copystr.S
index 7cd3571..0b95686 100644
--- a/sys/arm/arm/copystr.S
+++ b/sys/arm/arm/copystr.S
@@ -42,7 +42,6 @@
 #include "assym.s"
 #include <machine/asm.h>
 #include <machine/armreg.h>
-#include <machine/asmacros.h>
 __FBSDID("$FreeBSD$");
 
 #include <sys/errno.h>
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 44e81d8..3b9155f 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -1,9 +1,6 @@
 /*	$NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $	*/
 
 /*-
- * arm7tdmi support code Copyright (c) 2001 John Fremlin
- * arm8 support code Copyright (c) 1997 ARM Limited
- * arm8 support code Copyright (c) 1997 Causality Limited
  * arm9 support code Copyright (C) 2001 ARM Ltd
  * Copyright (c) 1997 Mark Brinicombe.
  * Copyright (c) 1997 Causality Limited
@@ -112,131 +109,6 @@ u_int	arm_cache_loc;
 int cpu_do_powersave;
 int ctrl;
 
-#ifdef CPU_ARM7TDMI
-struct cpu_functions arm7tdmi_cpufuncs = {
-	/* CPU functions */
-	
-	cpufunc_id,			/* id			*/
-	cpufunc_nullop,			/* cpwait		*/
-
-	/* MMU functions */
-
-	cpufunc_control,		/* control		*/
-	cpufunc_domains,		/* domain		*/
-	arm7tdmi_setttb,		/* setttb		*/
-	cpufunc_faultstatus,		/* faultstatus		*/
-	cpufunc_faultaddress,		/* faultaddress		*/
-
-	/* TLB functions */
-
-	arm7tdmi_tlb_flushID,		/* tlb_flushID		*/
-	arm7tdmi_tlb_flushID_SE,	/* tlb_flushID_SE	*/
-	arm7tdmi_tlb_flushID,		/* tlb_flushI		*/
-	arm7tdmi_tlb_flushID_SE,	/* tlb_flushI_SE	*/
-	arm7tdmi_tlb_flushID,		/* tlb_flushD		*/
-	arm7tdmi_tlb_flushID_SE,	/* tlb_flushD_SE	*/
-
-	/* Cache operations */
-
-	cpufunc_nullop,			/* icache_sync_all	*/
-	(void *)cpufunc_nullop,		/* icache_sync_range	*/
-
-	arm7tdmi_cache_flushID,		/* dcache_wbinv_all	*/
-	(void *)arm7tdmi_cache_flushID,	/* dcache_wbinv_range	*/
-	(void *)arm7tdmi_cache_flushID,	/* dcache_inv_range	*/
-	(void *)cpufunc_nullop,		/* dcache_wb_range	*/
-
-	cpufunc_nullop,			/* idcache_inv_all	*/
-	arm7tdmi_cache_flushID,		/* idcache_wbinv_all	*/
-	(void *)arm7tdmi_cache_flushID,	/* idcache_wbinv_range	*/
-	cpufunc_nullop,			/* l2cache_wbinv_all	*/
-	(void *)cpufunc_nullop,		/* l2cache_wbinv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_inv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_wb_range	*/
-
-	/* Other functions */
-
-	cpufunc_nullop,			/* flush_prefetchbuf	*/
-	cpufunc_nullop,			/* drain_writebuf	*/
-	cpufunc_nullop,			/* flush_brnchtgt_C	*/
-	(void *)cpufunc_nullop,		/* flush_brnchtgt_E	*/
-
-	(void *)cpufunc_nullop,		/* sleep		*/
-
-	/* Soft functions */
-
-	late_abort_fixup,		/* dataabt_fixup	*/
-	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
-
-	arm7tdmi_context_switch,	/* context_switch	*/
-
-	arm7tdmi_setup			/* cpu setup		*/
-
-};
-#endif	/* CPU_ARM7TDMI */
-
-#ifdef CPU_ARM8
-struct cpu_functions arm8_cpufuncs = {
-	/* CPU functions */
-	
-	cpufunc_id,			/* id			*/
-	cpufunc_nullop,			/* cpwait		*/
-
-	/* MMU functions */
-
-	cpufunc_control,		/* control		*/
-	cpufunc_domains,		/* domain		*/
-	arm8_setttb,			/* setttb		*/
-	cpufunc_faultstatus,		/* faultstatus		*/
-	cpufunc_faultaddress,		/* faultaddress		*/
-
-	/* TLB functions */
-
-	arm8_tlb_flushID,		/* tlb_flushID		*/
-	arm8_tlb_flushID_SE,		/* tlb_flushID_SE	*/
-	arm8_tlb_flushID,		/* tlb_flushI		*/
-	arm8_tlb_flushID_SE,		/* tlb_flushI_SE	*/
-	arm8_tlb_flushID,		/* tlb_flushD		*/
-	arm8_tlb_flushID_SE,		/* tlb_flushD_SE	*/
-
-	/* Cache operations */
-
-	cpufunc_nullop,			/* icache_sync_all	*/
-	(void *)cpufunc_nullop,		/* icache_sync_range	*/
-
-	arm8_cache_purgeID,		/* dcache_wbinv_all	*/
-	(void *)arm8_cache_purgeID,	/* dcache_wbinv_range	*/
-/*XXX*/	(void *)arm8_cache_purgeID,	/* dcache_inv_range	*/
-	(void *)arm8_cache_cleanID,	/* dcache_wb_range	*/
-
-	cpufunc_nullop,			/* idcache_inv_all	*/
-	arm8_cache_purgeID,		/* idcache_wbinv_all	*/
-	(void *)arm8_cache_purgeID,	/* idcache_wbinv_range	*/
-	cpufunc_nullop,			/* l2cache_wbinv_all	*/
-	(void *)cpufunc_nullop,		/* l2cache_wbinv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_inv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_wb_range	*/
-
-	/* Other functions */
-
-	cpufunc_nullop,			/* flush_prefetchbuf	*/
-	cpufunc_nullop,			/* drain_writebuf	*/
-	cpufunc_nullop,			/* flush_brnchtgt_C	*/
-	(void *)cpufunc_nullop,		/* flush_brnchtgt_E	*/
-
-	(void *)cpufunc_nullop,		/* sleep		*/
-
-	/* Soft functions */
-
-	cpufunc_null_fixup,		/* dataabt_fixup	*/
-	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
-
-	arm8_context_switch,		/* context_switch	*/
-
-	arm8_setup			/* cpu setup		*/
-};
-#endif	/* CPU_ARM8 */
-
 #ifdef CPU_ARM9
 struct cpu_functions arm9_cpufuncs = {
 	/* CPU functions */
@@ -550,192 +422,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
 };
 #endif /* CPU_MV_PJ4B */
 
-#ifdef CPU_SA110
-struct cpu_functions sa110_cpufuncs = {
-	/* CPU functions */
-	
-	cpufunc_id,			/* id			*/
-	cpufunc_nullop,			/* cpwait		*/
-
-	/* MMU functions */
-
-	cpufunc_control,		/* control		*/
-	cpufunc_domains,		/* domain		*/
-	sa1_setttb,			/* setttb		*/
-	cpufunc_faultstatus,		/* faultstatus		*/
-	cpufunc_faultaddress,		/* faultaddress		*/
-
-	/* TLB functions */
-
-	armv4_tlb_flushID,		/* tlb_flushID		*/
-	sa1_tlb_flushID_SE,		/* tlb_flushID_SE	*/
-	armv4_tlb_flushI,		/* tlb_flushI		*/
-	(void *)armv4_tlb_flushI,	/* tlb_flushI_SE	*/
-	armv4_tlb_flushD,		/* tlb_flushD		*/
-	armv4_tlb_flushD_SE,		/* tlb_flushD_SE	*/
-
-	/* Cache operations */
-
-	sa1_cache_syncI,		/* icache_sync_all	*/
-	sa1_cache_syncI_rng,		/* icache_sync_range	*/
-
-	sa1_cache_purgeD,		/* dcache_wbinv_all	*/
-	sa1_cache_purgeD_rng,		/* dcache_wbinv_range	*/
-/*XXX*/	sa1_cache_purgeD_rng,		/* dcache_inv_range	*/
-	sa1_cache_cleanD_rng,		/* dcache_wb_range	*/
-
-	sa1_cache_flushID,		/* idcache_inv_all	*/
-	sa1_cache_purgeID,		/* idcache_wbinv_all	*/
-	sa1_cache_purgeID_rng,		/* idcache_wbinv_range	*/
-	cpufunc_nullop,			/* l2cache_wbinv_all	*/
-	(void *)cpufunc_nullop,		/* l2cache_wbinv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_inv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_wb_range	*/
-
-	/* Other functions */
-
-	cpufunc_nullop,			/* flush_prefetchbuf	*/
-	armv4_drain_writebuf,		/* drain_writebuf	*/
-	cpufunc_nullop,			/* flush_brnchtgt_C	*/
-	(void *)cpufunc_nullop,		/* flush_brnchtgt_E	*/
-
-	(void *)cpufunc_nullop,		/* sleep		*/
-
-	/* Soft functions */
-
-	cpufunc_null_fixup,		/* dataabt_fixup	*/
-	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
-
-	sa110_context_switch,		/* context_switch	*/
-
-	sa110_setup			/* cpu setup		*/
-};
-#endif	/* CPU_SA110 */
-
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-struct cpu_functions sa11x0_cpufuncs = {
-	/* CPU functions */
-	
-	cpufunc_id,			/* id			*/
-	cpufunc_nullop,			/* cpwait		*/
-
-	/* MMU functions */
-
-	cpufunc_control,		/* control		*/
-	cpufunc_domains,		/* domain		*/
-	sa1_setttb,			/* setttb		*/
-	cpufunc_faultstatus,		/* faultstatus		*/
-	cpufunc_faultaddress,		/* faultaddress		*/
-
-	/* TLB functions */
-
-	armv4_tlb_flushID,		/* tlb_flushID		*/
-	sa1_tlb_flushID_SE,		/* tlb_flushID_SE	*/
-	armv4_tlb_flushI,		/* tlb_flushI		*/
-	(void *)armv4_tlb_flushI,	/* tlb_flushI_SE	*/
-	armv4_tlb_flushD,		/* tlb_flushD		*/
-	armv4_tlb_flushD_SE,		/* tlb_flushD_SE	*/
-
-	/* Cache operations */
-
-	sa1_cache_syncI,		/* icache_sync_all	*/
-	sa1_cache_syncI_rng,		/* icache_sync_range	*/
-
-	sa1_cache_purgeD,		/* dcache_wbinv_all	*/
-	sa1_cache_purgeD_rng,		/* dcache_wbinv_range	*/
-/*XXX*/	sa1_cache_purgeD_rng,		/* dcache_inv_range	*/
-	sa1_cache_cleanD_rng,		/* dcache_wb_range	*/
-
-	sa1_cache_flushID,		/* idcache_inv_all	*/
-	sa1_cache_purgeID,		/* idcache_wbinv_all	*/
-	sa1_cache_purgeID_rng,		/* idcache_wbinv_range	*/
-	cpufunc_nullop,			/* l2cache_wbinv_all	*/
-	(void *)cpufunc_nullop,		/* l2cache_wbinv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_inv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_wb_range	*/
-
-	/* Other functions */
-
-	sa11x0_drain_readbuf,		/* flush_prefetchbuf	*/
-	armv4_drain_writebuf,		/* drain_writebuf	*/
-	cpufunc_nullop,			/* flush_brnchtgt_C	*/
-	(void *)cpufunc_nullop,		/* flush_brnchtgt_E	*/
-
-	sa11x0_cpu_sleep,		/* sleep		*/
-
-	/* Soft functions */
-
-	cpufunc_null_fixup,		/* dataabt_fixup	*/
-	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
-
-	sa11x0_context_switch,		/* context_switch	*/
-
-	sa11x0_setup			/* cpu setup		*/
-};
-#endif	/* CPU_SA1100 || CPU_SA1110 */
-
-#ifdef CPU_IXP12X0
-struct cpu_functions ixp12x0_cpufuncs = {
-	/* CPU functions */
-	
-	cpufunc_id,			/* id			*/
-	cpufunc_nullop,			/* cpwait		*/
-
-	/* MMU functions */
-
-	cpufunc_control,		/* control		*/
-	cpufunc_domains,		/* domain		*/
-	sa1_setttb,			/* setttb		*/
-	cpufunc_faultstatus,		/* faultstatus		*/
-	cpufunc_faultaddress,		/* faultaddress		*/
-
-	/* TLB functions */
-
-	armv4_tlb_flushID,		/* tlb_flushID		*/
-	sa1_tlb_flushID_SE,		/* tlb_flushID_SE	*/
-	armv4_tlb_flushI,		/* tlb_flushI		*/
-	(void *)armv4_tlb_flushI,	/* tlb_flushI_SE	*/
-	armv4_tlb_flushD,		/* tlb_flushD		*/
-	armv4_tlb_flushD_SE,		/* tlb_flushD_SE	*/
-
-	/* Cache operations */
-
-	sa1_cache_syncI,		/* icache_sync_all	*/
-	sa1_cache_syncI_rng,		/* icache_sync_range	*/
-
-	sa1_cache_purgeD,		/* dcache_wbinv_all	*/
-	sa1_cache_purgeD_rng,		/* dcache_wbinv_range	*/
-/*XXX*/	sa1_cache_purgeD_rng,		/* dcache_inv_range	*/
-	sa1_cache_cleanD_rng,		/* dcache_wb_range	*/
-
-	sa1_cache_flushID,		/* idcache_inv_all	*/
-	sa1_cache_purgeID,		/* idcache_wbinv_all	*/
-	sa1_cache_purgeID_rng,		/* idcache_wbinv_range	*/
-	cpufunc_nullop,			/* l2cache_wbinv_all	*/
-	(void *)cpufunc_nullop,		/* l2cache_wbinv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_inv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_wb_range	*/
-
-	/* Other functions */
-
-	ixp12x0_drain_readbuf,			/* flush_prefetchbuf	*/
-	armv4_drain_writebuf,		/* drain_writebuf	*/
-	cpufunc_nullop,			/* flush_brnchtgt_C	*/
-	(void *)cpufunc_nullop,		/* flush_brnchtgt_E	*/
-
-	(void *)cpufunc_nullop,		/* sleep		*/
-
-	/* Soft functions */
-
-	cpufunc_null_fixup,		/* dataabt_fixup	*/
-	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
-
-	ixp12x0_context_switch,		/* context_switch	*/
-
-	ixp12x0_setup			/* cpu setup		*/
-};
-#endif	/* CPU_IXP12X0 */
-
 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
   defined(CPU_XSCALE_80219)
@@ -1128,7 +814,7 @@ struct cpu_functions cpufuncs;
 u_int cputype;
 u_int cpu_reset_needs_v4_MMU_disable;	/* flag used in locore.s */
 
-#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) ||	\
+#if defined(CPU_ARM9) ||	\
   defined (CPU_ARM9E) || defined (CPU_ARM10) || defined (CPU_ARM1136) ||	\
   defined(CPU_ARM1176) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
@@ -1247,61 +933,7 @@ get_cachetype_cp15()
 		arm_dcache_align_mask = arm_dcache_align - 1;
 	}
 }
-#endif /* ARM7TDMI || ARM8 || ARM9 || XSCALE */
-
-#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
-    defined(CPU_IXP12X0)
-/* Cache information for CPUs without cache type registers. */
-struct cachetab {
-	u_int32_t ct_cpuid;
-	int	ct_pcache_type;
-	int	ct_pcache_unified;
-	int	ct_pdcache_size;
-	int	ct_pdcache_line_size;
-	int	ct_pdcache_ways;
-	int	ct_picache_size;
-	int	ct_picache_line_size;
-	int	ct_picache_ways;
-};
-
-struct cachetab cachetab[] = {
-    /* cpuid,           cache type,       u,  dsiz, ls, wy,  isiz, ls, wy */
-    /* XXX is this type right for SA-1? */
-    { CPU_ID_SA110,	CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 },
-    { CPU_ID_SA1100,	CPU_CT_CTYPE_WB1, 0,  8192, 32, 32, 16384, 32, 32 },
-    { CPU_ID_SA1110,	CPU_CT_CTYPE_WB1, 0,  8192, 32, 32, 16384, 32, 32 },
-    { CPU_ID_IXP1200,	CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 }, /* XXX */
-    { 0, 0, 0, 0, 0, 0, 0, 0}
-};
-
-static void get_cachetype_table(void);
-
-static void
-get_cachetype_table()
-{
-	int i;
-	u_int32_t cpuid = cpufunc_id();
-
-	for (i = 0; cachetab[i].ct_cpuid != 0; i++) {
-		if (cachetab[i].ct_cpuid == (cpuid & CPU_ID_CPU_MASK)) {
-			arm_pcache_type = cachetab[i].ct_pcache_type;
-			arm_pcache_unified = cachetab[i].ct_pcache_unified;
-			arm_pdcache_size = cachetab[i].ct_pdcache_size;
-			arm_pdcache_line_size =
-			    cachetab[i].ct_pdcache_line_size;
-			arm_pdcache_ways = cachetab[i].ct_pdcache_ways;
-			arm_picache_size = cachetab[i].ct_picache_size;
-			arm_picache_line_size =
-			    cachetab[i].ct_picache_line_size;
-			arm_picache_ways = cachetab[i].ct_picache_ways;
-		}
-	}
-	arm_dcache_align = arm_pdcache_line_size;
-
-	arm_dcache_align_mask = arm_dcache_align - 1;
-}
-
-#endif /* SA110 || SA1100 || SA1111 || IXP12X0 */
+#endif /* ARM9 || XSCALE */
 
 /*
  * Cannot panic here as we may not have a console yet ...
@@ -1318,27 +950,6 @@ set_cpufuncs()
 	 * CPU type where we want to use it by default, then we set it.
 	 */
 
-#ifdef CPU_ARM7TDMI
-	if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
-	    CPU_ID_IS7(cputype) &&
-	    (cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V4T) {
-		cpufuncs = arm7tdmi_cpufuncs;
-		cpu_reset_needs_v4_MMU_disable = 0;
-		get_cachetype_cp15();
-		pmap_pte_init_generic();
-		goto out;
-	}
-#endif	
-#ifdef CPU_ARM8
-	if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
-	    (cputype & 0x0000f000) == 0x00008000) {
-		cpufuncs = arm8_cpufuncs;
-		cpu_reset_needs_v4_MMU_disable = 0;	/* XXX correct? */
-		get_cachetype_cp15();
-		pmap_pte_init_arm8();
-		goto out;
-	}
-#endif	/* CPU_ARM8 */
 #ifdef CPU_ARM9
 	if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD ||
 	     (cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) &&
@@ -1463,39 +1074,7 @@ set_cpufuncs()
 		goto out;
 	}
 #endif /* CPU_MV_PJ4B */
-#ifdef CPU_SA110
-	if (cputype == CPU_ID_SA110) {
-		cpufuncs = sa110_cpufuncs;
-		cpu_reset_needs_v4_MMU_disable = 1;	/* SA needs it */
-		get_cachetype_table();
-		pmap_pte_init_sa1();
-		goto out;
-	}
-#endif	/* CPU_SA110 */
-#ifdef CPU_SA1100
-	if (cputype == CPU_ID_SA1100) {
-		cpufuncs = sa11x0_cpufuncs;
-		cpu_reset_needs_v4_MMU_disable = 1;	/* SA needs it	*/
-		get_cachetype_table();
-		pmap_pte_init_sa1();
-		/* Use powersave on this CPU. */
-		cpu_do_powersave = 1;
 
-		goto out;
-	}
-#endif	/* CPU_SA1100 */
-#ifdef CPU_SA1110
-	if (cputype == CPU_ID_SA1110) {
-		cpufuncs = sa11x0_cpufuncs;
-		cpu_reset_needs_v4_MMU_disable = 1;	/* SA needs it	*/
-		get_cachetype_table();
-		pmap_pte_init_sa1();
-		/* Use powersave on this CPU. */
-		cpu_do_powersave = 1;
-
-		goto out;
-	}
-#endif	/* CPU_SA1110 */
 #if defined(CPU_FA526) || defined(CPU_FA626TE)
 	if (cputype == CPU_ID_FA526 || cputype == CPU_ID_FA626TE) {
 		cpufuncs = fa526_cpufuncs;
@@ -1509,15 +1088,7 @@ set_cpufuncs()
 		goto out;
 	}
 #endif	/* CPU_FA526 || CPU_FA626TE */
-#ifdef CPU_IXP12X0
-        if (cputype == CPU_ID_IXP1200) {
-                cpufuncs = ixp12x0_cpufuncs;
-                cpu_reset_needs_v4_MMU_disable = 1;
-                get_cachetype_table();
-                pmap_pte_init_sa1();
-		goto out;
-        }
-#endif  /* CPU_IXP12X0 */
+
 #ifdef CPU_XSCALE_80200
 	if (cputype == CPU_ID_80200) {
 		int rev = cpufunc_id() & CPU_ID_REVISION_MASK;
@@ -1626,8 +1197,6 @@ out:
  *
  * DEBUG_FAULT_CORRECTION - Print debugging information during the
  * correction of registers after a fault.
- * ARM6_LATE_ABORT - ARM6 supports both early and late aborts
- * when defined should use late aborts
  */
 
 
@@ -1642,344 +1211,12 @@ cpufunc_null_fixup(arg)
 	return(ABORT_FIXUP_OK);
 }
 
-
-#if defined(CPU_ARM7TDMI)
-
-#ifdef DEBUG_FAULT_CORRECTION
-#define DFC_PRINTF(x)		printf x
-#define DFC_DISASSEMBLE(x)	disassemble(x)
-#else
-#define DFC_PRINTF(x)		/* nothing */
-#define DFC_DISASSEMBLE(x)	/* nothing */
-#endif
-
-/*
- * "Early" data abort fixup.
- *
- * For ARM2, ARM2as, ARM3 and ARM6 (in early-abort mode).  Also used
- * indirectly by ARM6 (in late-abort mode) and ARM7[TDMI].
- *
- * In early aborts, we may have to fix up LDM, STM, LDC and STC.
- */
-int
-early_abort_fixup(arg)
-	void *arg;
-{
-	struct trapframe *frame = arg;
-	u_int fault_pc;
-	u_int fault_instruction;
-	int saved_lr = 0;
-
-	if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
-
-		/* Ok an abort in SVC mode */
-
-		/*
-		 * Copy the SVC r14 into the usr r14 - The usr r14 is garbage
-		 * as the fault happened in svc mode but we need it in the
-		 * usr slot so we can treat the registers as an array of ints
-		 * during fixing.
-		 * NOTE: This PC is in the position but writeback is not
-		 * allowed on r15.
-		 * Doing it like this is more efficient than trapping this
-		 * case in all possible locations in the following fixup code.
-		 */
-
-		saved_lr = frame->tf_usr_lr;
-		frame->tf_usr_lr = frame->tf_svc_lr;
-
-		/*
-		 * Note the trapframe does not have the SVC r13 so a fault
-		 * from an instruction with writeback to r13 in SVC mode is
-		 * not allowed. This should not happen as the kstack is
-		 * always valid.
-		 */
-	}
-
-	/* Get fault address and status from the CPU */
-
-	fault_pc = frame->tf_pc;
-	fault_instruction = *((volatile unsigned int *)fault_pc);
-
-	/* Decode the fault instruction and fix the registers as needed */
-
-	if ((fault_instruction & 0x0e000000) == 0x08000000) {
-		int base;
-		int loop;
-		int count;
-		int *registers = &frame->tf_r0;
-
-		DFC_PRINTF(("LDM/STM\n"));
-		DFC_DISASSEMBLE(fault_pc);
-		if (fault_instruction & (1 << 21)) {
-			DFC_PRINTF(("This instruction must be corrected\n"));
-			base = (fault_instruction >> 16) & 0x0f;
-			if (base == 15)
-				return ABORT_FIXUP_FAILED;
-			/* Count registers transferred */
-			count = 0;
-			for (loop = 0; loop < 16; ++loop) {
-				if (fault_instruction & (1<<loop))
-					++count;
-			}
-			DFC_PRINTF(("%d registers used\n", count));
-			DFC_PRINTF(("Corrected r%d by %d bytes ",
-				       base, count * 4));
-			if (fault_instruction & (1 << 23)) {
-				DFC_PRINTF(("down\n"));
-				registers[base] -= count * 4;
-			} else {
-				DFC_PRINTF(("up\n"));
-				registers[base] += count * 4;
-			}
-		}
-	} else if ((fault_instruction & 0x0e000000) == 0x0c000000) {
-		int base;
-		int offset;
-		int *registers = &frame->tf_r0;
-	
-		/* REGISTER CORRECTION IS REQUIRED FOR THESE INSTRUCTIONS */
-
-		DFC_DISASSEMBLE(fault_pc);
-
-		/* Only need to fix registers if write back is turned on */
-
-		if ((fault_instruction & (1 << 21)) != 0) {
-			base = (fault_instruction >> 16) & 0x0f;
-			if (base == 13 &&
-			    (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE)
-				return ABORT_FIXUP_FAILED;
-			if (base == 15)
-				return ABORT_FIXUP_FAILED;
-
-			offset = (fault_instruction & 0xff) << 2;
-			DFC_PRINTF(("r%d=%08x\n", base, registers[base]));
-			if ((fault_instruction & (1 << 23)) != 0)
-				offset = -offset;
-			registers[base] += offset;
-			DFC_PRINTF(("r%d=%08x\n", base, registers[base]));
-		}
-	} else if ((fault_instruction & 0x0e000000) == 0x0c000000)
-		return ABORT_FIXUP_FAILED;
-
-	if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
-
-		/* Ok an abort in SVC mode */
-
-		/*
-		 * Copy the SVC r14 into the usr r14 - The usr r14 is garbage
-		 * as the fault happened in svc mode but we need it in the
-		 * usr slot so we can treat the registers as an array of ints
-		 * during fixing.
-		 * NOTE: This PC is in the position but writeback is not
-		 * allowed on r15.
-		 * Doing it like this is more efficient than trapping this
-		 * case in all possible locations in the prior fixup code.
-		 */
-
-		frame->tf_svc_lr = frame->tf_usr_lr;
-		frame->tf_usr_lr = saved_lr;
-
-		/*
-		 * Note the trapframe does not have the SVC r13 so a fault
-		 * from an instruction with writeback to r13 in SVC mode is
-		 * not allowed. This should not happen as the kstack is
-		 * always valid.
-		 */
-	}
-
-	return(ABORT_FIXUP_OK);
-}
-#endif	/* CPU_ARM2/250/3/6/7 */
-
-
-#if defined(CPU_ARM7TDMI)
-/*
- * "Late" (base updated) data abort fixup
- *
- * For ARM6 (in late-abort mode) and ARM7.
- *
- * In this model, all data-transfer instructions need fixing up.  We defer
- * LDM, STM, LDC and STC fixup to the early-abort handler.
- */
-int
-late_abort_fixup(arg)
-	void *arg;
-{
-	struct trapframe *frame = arg;
-	u_int fault_pc;
-	u_int fault_instruction;
-	int saved_lr = 0;
-
-	if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
-
-		/* Ok an abort in SVC mode */
-
-		/*
-		 * Copy the SVC r14 into the usr r14 - The usr r14 is garbage
-		 * as the fault happened in svc mode but we need it in the
-		 * usr slot so we can treat the registers as an array of ints
-		 * during fixing.
-		 * NOTE: This PC is in the position but writeback is not
-		 * allowed on r15.
-		 * Doing it like this is more efficient than trapping this
-		 * case in all possible locations in the following fixup code.
-		 */
-
-		saved_lr = frame->tf_usr_lr;
-		frame->tf_usr_lr = frame->tf_svc_lr;
-
-		/*
-		 * Note the trapframe does not have the SVC r13 so a fault
-		 * from an instruction with writeback to r13 in SVC mode is
-		 * not allowed. This should not happen as the kstack is
-		 * always valid.
-		 */
-	}
-
-	/* Get fault address and status from the CPU */
-
-	fault_pc = frame->tf_pc;
-	fault_instruction = *((volatile unsigned int *)fault_pc);
-
-	/* Decode the fault instruction and fix the registers as needed */
-
-	/* Was is a swap instruction ? */
-
-	if ((fault_instruction & 0x0fb00ff0) == 0x01000090) {
-		DFC_DISASSEMBLE(fault_pc);
-	} else if ((fault_instruction & 0x0c000000) == 0x04000000) {
-
-		/* Was is a ldr/str instruction */
-		/* This is for late abort only */
-
-		int base;
-		int offset;
-		int *registers = &frame->tf_r0;
-
-		DFC_DISASSEMBLE(fault_pc);
-		
-		/* This is for late abort only */
-
-		if ((fault_instruction & (1 << 24)) == 0
-		    || (fault_instruction & (1 << 21)) != 0) {	
-			/* postindexed ldr/str with no writeback */
-
-			base = (fault_instruction >> 16) & 0x0f;
-			if (base == 13 &&
-			    (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE)
-				return ABORT_FIXUP_FAILED;
-			if (base == 15)
-				return ABORT_FIXUP_FAILED;
-			DFC_PRINTF(("late abt fix: r%d=%08x : ",
-				       base, registers[base]));
-			if ((fault_instruction & (1 << 25)) == 0) {
-				/* Immediate offset - easy */
-
-				offset = fault_instruction & 0xfff;
-				if ((fault_instruction & (1 << 23)))
-					offset = -offset;
-				registers[base] += offset;
-				DFC_PRINTF(("imm=%08x ", offset));
-			} else {
-				/* offset is a shifted register */
-				int shift;
-
-				offset = fault_instruction & 0x0f;
-				if (offset == base)
-					return ABORT_FIXUP_FAILED;
-
-				/*
-				 * Register offset - hard we have to
-				 * cope with shifts !
-				 */
-				offset = registers[offset];
-
-				if ((fault_instruction & (1 << 4)) == 0)
-					/* shift with amount */
-					shift = (fault_instruction >> 7) & 0x1f;
-				else {
-					/* shift with register */
-					if ((fault_instruction & (1 << 7)) != 0)
-						/* undefined for now so bail out */
-						return ABORT_FIXUP_FAILED;
-					shift = ((fault_instruction >> 8) & 0xf);
-					if (base == shift)
-						return ABORT_FIXUP_FAILED;
-					DFC_PRINTF(("shift reg=%d ", shift));
-					shift = registers[shift];
-				}
-				DFC_PRINTF(("shift=%08x ", shift));
-				switch (((fault_instruction >> 5) & 0x3)) {
-				case 0 : /* Logical left */
-					offset = (int)(((u_int)offset) << shift);
-					break;
-				case 1 : /* Logical Right */
-					if (shift == 0) shift = 32;
-					offset = (int)(((u_int)offset) >> shift);
-					break;
-				case 2 : /* Arithmetic Right */
-					if (shift == 0) shift = 32;
-					offset = (int)(((int)offset) >> shift);
-					break;
-				case 3 : /* Rotate right (rol or rxx) */
-					return ABORT_FIXUP_FAILED;
-					break;
-				}
-
-				DFC_PRINTF(("abt: fixed LDR/STR with "
-					       "register offset\n"));
-				if ((fault_instruction & (1 << 23)))
-					offset = -offset;
-				DFC_PRINTF(("offset=%08x ", offset));
-				registers[base] += offset;
-			}
-			DFC_PRINTF(("r%d=%08x\n", base, registers[base]));
-		}
-	}
-
-	if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
-
-		/* Ok an abort in SVC mode */
-
-		/*
-		 * Copy the SVC r14 into the usr r14 - The usr r14 is garbage
-		 * as the fault happened in svc mode but we need it in the
-		 * usr slot so we can treat the registers as an array of ints
-		 * during fixing.
-		 * NOTE: This PC is in the position but writeback is not
-		 * allowed on r15.
-		 * Doing it like this is more efficient than trapping this
-		 * case in all possible locations in the prior fixup code.
-		 */
-
-		frame->tf_svc_lr = frame->tf_usr_lr;
-		frame->tf_usr_lr = saved_lr;
-
-		/*
-		 * Note the trapframe does not have the SVC r13 so a fault
-		 * from an instruction with writeback to r13 in SVC mode is
-		 * not allowed. This should not happen as the kstack is
-		 * always valid.
-		 */
-	}
-
-	/*
-	 * Now let the early-abort fixup routine have a go, in case it
-	 * was an LDM, STM, LDC or STC that faulted.
-	 */
-
-	return early_abort_fixup(arg);
-}
-#endif	/* CPU_ARM7TDMI */
-
 /*
  * CPU Setup code
  */
 
-#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined (CPU_ARM9) || \
+#if defined (CPU_ARM9) || \
   defined(CPU_ARM9E) || \
-  defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||	\
   defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
   defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
@@ -2029,148 +1266,7 @@ parse_cpu_options(args, optlist, cpuctrl)
 	}
 	return(cpuctrl);
 }
-#endif /* CPU_ARM7TDMI || CPU_ARM8 || CPU_SA110 || XSCALE*/
-
-#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8)
-struct cpu_option arm678_options[] = {
-#ifdef COMPAT_12
-	{ "nocache",		IGN, BIC, CPU_CONTROL_IDC_ENABLE },
-	{ "nowritebuf",		IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
-#endif	/* COMPAT_12 */
-	{ "cpu.cache",		BIC, OR,  CPU_CONTROL_IDC_ENABLE },
-	{ "cpu.nocache",	OR,  BIC, CPU_CONTROL_IDC_ENABLE },
-	{ "cpu.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ "cpu.nowritebuf",	OR,  BIC, CPU_CONTROL_WBUF_ENABLE },
-	{ NULL,			IGN, IGN, 0 }
-};
-
-#endif	/* CPU_ARM6 || CPU_ARM7 || CPU_ARM7TDMI || CPU_ARM8 */
-
-#ifdef CPU_ARM7TDMI
-struct cpu_option arm7tdmi_options[] = {
-	{ "arm7.cache",		BIC, OR,  CPU_CONTROL_IDC_ENABLE },
-	{ "arm7.nocache",	OR,  BIC, CPU_CONTROL_IDC_ENABLE },
-	{ "arm7.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ "arm7.nowritebuf",	OR,  BIC, CPU_CONTROL_WBUF_ENABLE },
-#ifdef COMPAT_12
-	{ "fpaclk2",		BIC, OR,  CPU_CONTROL_CPCLK },
-#endif	/* COMPAT_12 */
-	{ "arm700.fpaclk",	BIC, OR,  CPU_CONTROL_CPCLK },
-	{ NULL,			IGN, IGN, 0 }
-};
-
-void
-arm7tdmi_setup(args)
-	char *args;
-{
-	int cpuctrl;
-
-	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
-		 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
-
-	cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl);
-	cpuctrl = parse_cpu_options(args, arm7tdmi_options, cpuctrl);
-
-#ifdef __ARMEB__
-	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
-	/* Clear out the cache */
-	cpu_idcache_wbinv_all();
-
-	/* Set the control register */
-	ctrl = cpuctrl;
-	cpu_control(0xffffffff, cpuctrl);
-}
-#endif	/* CPU_ARM7TDMI */
-
-#ifdef CPU_ARM8
-struct cpu_option arm8_options[] = {
-	{ "arm8.cache",		BIC, OR,  CPU_CONTROL_IDC_ENABLE },
-	{ "arm8.nocache",	OR,  BIC, CPU_CONTROL_IDC_ENABLE },
-	{ "arm8.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ "arm8.nowritebuf",	OR,  BIC, CPU_CONTROL_WBUF_ENABLE },
-#ifdef COMPAT_12
-	{ "branchpredict", 	BIC, OR,  CPU_CONTROL_BPRD_ENABLE },
-#endif	/* COMPAT_12 */
-	{ "cpu.branchpredict", 	BIC, OR,  CPU_CONTROL_BPRD_ENABLE },
-	{ "arm8.branchpredict",	BIC, OR,  CPU_CONTROL_BPRD_ENABLE },
-	{ NULL,			IGN, IGN, 0 }
-};
-
-void
-arm8_setup(args)
-	char *args;
-{
-	int integer;
-	int cpuctrl, cpuctrlmask;
-	int clocktest;
-	int setclock = 0;
-
-	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
-		 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
-	cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
-		 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
-		 | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_ROM_ENABLE
-		 | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE;
-
-#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
-	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
-#endif
-
-	cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl);
-	cpuctrl = parse_cpu_options(args, arm8_options, cpuctrl);
-
-#ifdef __ARMEB__
-	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
-	/* Get clock configuration */
-	clocktest = arm8_clock_config(0, 0) & 0x0f;
-
-	/* Special ARM8 clock and test configuration */
-	if (get_bootconf_option(args, "arm8.clock.reset", BOOTOPT_TYPE_BOOLEAN, &integer)) {
-		clocktest = 0;
-		setclock = 1;
-	}
-	if (get_bootconf_option(args, "arm8.clock.dynamic", BOOTOPT_TYPE_BOOLEAN, &integer)) {
-		if (integer)
-			clocktest |= 0x01;
-		else
-			clocktest &= ~(0x01);
-		setclock = 1;
-	}
-	if (get_bootconf_option(args, "arm8.clock.sync", BOOTOPT_TYPE_BOOLEAN, &integer)) {
-		if (integer)
-			clocktest |= 0x02;
-		else
-			clocktest &= ~(0x02);
-		setclock = 1;
-	}
-	if (get_bootconf_option(args, "arm8.clock.fast", BOOTOPT_TYPE_BININT, &integer)) {
-		clocktest = (clocktest & ~0xc0) | (integer & 3) << 2;
-		setclock = 1;
-	}
-	if (get_bootconf_option(args, "arm8.test", BOOTOPT_TYPE_BININT, &integer)) {
-		clocktest |= (integer & 7) << 5;
-		setclock = 1;
-	}
-	
-	/* Clear out the cache */
-	cpu_idcache_wbinv_all();
-
-	/* Set the control register */
-	ctrl = cpuctrl;
-	cpu_control(0xffffffff, cpuctrl);
-
-	/* Set the clock/test register */
-	if (setclock)
-		arm8_clock_config(0x7f, clocktest);
-}
-#endif	/* CPU_ARM8 */
+#endif /* CPU_ARM9 || XSCALE*/
 
 #ifdef CPU_ARM9
 struct cpu_option arm9_options[] = {
@@ -2470,124 +1566,6 @@ cortexa_setup(char *args)
 }
 #endif  /* CPU_CORTEXA */
 
-
-#ifdef CPU_SA110
-struct cpu_option sa110_options[] = {
-#ifdef COMPAT_12
-	{ "nocache",		IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "nowritebuf",		IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
-#endif	/* COMPAT_12 */
-	{ "cpu.cache",		BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "cpu.nocache",	OR,  BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "sa110.cache",	BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "sa110.icache",	BIC, OR,  CPU_CONTROL_IC_ENABLE },
-	{ "sa110.dcache",	BIC, OR,  CPU_CONTROL_DC_ENABLE },
-	{ "cpu.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ "cpu.nowritebuf",	OR,  BIC, CPU_CONTROL_WBUF_ENABLE },
-	{ "sa110.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ NULL,			IGN, IGN, 0 }
-};
-
-void
-sa110_setup(args)
-	char *args;
-{
-	int cpuctrl, cpuctrlmask;
-
-	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
-		 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
-		 | CPU_CONTROL_WBUF_ENABLE;
-	cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
-		 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
-		 | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
-		 | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
-		 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
-		 | CPU_CONTROL_CPCLK;
-
-#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
-	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
-#endif
-
-	cpuctrl = parse_cpu_options(args, sa110_options, cpuctrl);
-
-#ifdef __ARMEB__
-	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
-	/* Clear out the cache */
-	cpu_idcache_wbinv_all();
-
-	/* Set the control register */
-	ctrl = cpuctrl;
-/*	cpu_control(cpuctrlmask, cpuctrl);*/
-	cpu_control(0xffffffff, cpuctrl);
-
-	/*
-	 * enable clockswitching, note that this doesn't read or write to r0,
-	 * r0 is just to make it valid asm
-	 */
-	__asm ("mcr 15, 0, r0, c15, c1, 2");
-}
-#endif	/* CPU_SA110 */
-
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-struct cpu_option sa11x0_options[] = {
-#ifdef COMPAT_12
-	{ "nocache",		IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "nowritebuf",		IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
-#endif	/* COMPAT_12 */
-	{ "cpu.cache",		BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "cpu.nocache",	OR,  BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "sa11x0.cache",	BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "sa11x0.icache",	BIC, OR,  CPU_CONTROL_IC_ENABLE },
-	{ "sa11x0.dcache",	BIC, OR,  CPU_CONTROL_DC_ENABLE },
-	{ "cpu.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ "cpu.nowritebuf",	OR,  BIC, CPU_CONTROL_WBUF_ENABLE },
-	{ "sa11x0.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ NULL,			IGN, IGN, 0 }
-};
-
-void
-sa11x0_setup(args)
-	char *args;
-{
-	int cpuctrl, cpuctrlmask;
-
-	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
-		 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
-		 | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE;
-	cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
-		 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
-		 | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
-		 | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
-		 | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
-		 | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
-
-#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
-	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
-#endif
-
-
-	cpuctrl = parse_cpu_options(args, sa11x0_options, cpuctrl);
-
-#ifdef __ARMEB__
-	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
-	if (vector_page == ARM_VECTORS_HIGH)
-		cpuctrl |= CPU_CONTROL_VECRELOC;
-	/* Clear out the cache */
-	cpu_idcache_wbinv_all();
-	/* Set the control register */
-	ctrl = cpuctrl;
-	cpu_control(0xffffffff, cpuctrl);
-}
-#endif	/* CPU_SA1100 || CPU_SA1110 */
-
 #if defined(CPU_FA526) || defined(CPU_FA626TE)
 struct cpu_option fa526_options[] = {
 #ifdef COMPAT_12
@@ -2644,60 +1622,6 @@ fa526_setup(char *args)
 }
 #endif	/* CPU_FA526 || CPU_FA626TE */
 
-
-#if defined(CPU_IXP12X0)
-struct cpu_option ixp12x0_options[] = {
-	{ "cpu.cache",		BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "cpu.nocache",	OR,  BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "ixp12x0.cache",	BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
-	{ "ixp12x0.icache",	BIC, OR,  CPU_CONTROL_IC_ENABLE },
-	{ "ixp12x0.dcache",	BIC, OR,  CPU_CONTROL_DC_ENABLE },
-	{ "cpu.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ "cpu.nowritebuf",	OR,  BIC, CPU_CONTROL_WBUF_ENABLE },
-	{ "ixp12x0.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
-	{ NULL,			IGN, IGN, 0 }
-};
-
-void
-ixp12x0_setup(args)
-	char *args;
-{
-	int cpuctrl, cpuctrlmask;
-
-
-	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE
-		 | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_IC_ENABLE;
-
-	cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_AFLT_ENABLE
-		 | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE
-		 | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_SYST_ENABLE
-		 | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE
-		 | CPU_CONTROL_VECRELOC;
-
-#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
-	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
-#endif
-
-	cpuctrl = parse_cpu_options(args, ixp12x0_options, cpuctrl);
-
-#ifdef __ARMEB__
-	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
-	if (vector_page == ARM_VECTORS_HIGH)
-		cpuctrl |= CPU_CONTROL_VECRELOC;
-
-	/* Clear out the cache */
-	cpu_idcache_wbinv_all();
-
-	/* Set the control register */
-	ctrl = cpuctrl;
-	/* cpu_control(0xffffffff, cpuctrl); */
-	cpu_control(cpuctrlmask, cpuctrl);
-}
-#endif /* CPU_IXP12X0 */
-
 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
   defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
diff --git a/sys/arm/arm/cpufunc_asm_arm7tdmi.S b/sys/arm/arm/cpufunc_asm_arm7tdmi.S
deleted file mode 100644
index 2ac2502..0000000
--- a/sys/arm/arm/cpufunc_asm_arm7tdmi.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*	$NetBSD: cpufunc_asm_arm7tdmi.S,v 1.1 2001/11/10 23:14:09 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2001 John Fremlin
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Causality Limited.
- * 4. The name of Causality Limited may not be used to endorse or promote
- *    products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * ARM7TDMI assembly functions for CPU / MMU / TLB specific operations
- *
- */
-
-#include <machine/asm.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * Functions to set the MMU Translation Table Base register
- *
- * We need to clean and flush the cache as it uses virtual
- * addresses that are about to change.
- */
-ENTRY(arm7tdmi_setttb)
-	mov	r1, r0		/* store the TTB in a safe place */
-	mov	r2, lr		/* ditto with lr */
-
-	bl	_C_LABEL(arm7tdmi_cache_flushID)
-
-	/* Write the TTB */
-	mcr	p15, 0, r1, c2, c0, 0
-
-	/* If we have updated the TTB we must flush the TLB */
-	bl	_C_LABEL(arm7tdmi_tlb_flushID)
-
-	/* For good measure we will flush the IDC as well */
-	bl	_C_LABEL(arm7tdmi_cache_flushID)
-
-	mov	pc, r2
-END(arm7tdmi_setttb)
-
-/*
- * TLB functions
- */
-ENTRY(arm7tdmi_tlb_flushID)
-	mov	r0, #0
-	mcr	p15, 0, r0, c8, c7, 0
-	RET
-END(arm7tdmi_tlb_flushID)
-
-ENTRY(arm7tdmi_tlb_flushID_SE)
-	mcr	p15, 0, r0, c8, c7, 1
-	RET
-END(arm7tdmi_tlb_flushID_SE)
-
-/*
- * Cache functions
- */
-ENTRY(arm7tdmi_cache_flushID)
-	mov	r0, #0
-
-	mcr	p15, 0, r0, c7, c7, 0
-
-	/* Make sure that the pipeline is emptied */
-	mov	r0, r0
-	mov	r0, r0
-
-	RET
-END(arm7tdmi_cache_flushID)
-
-/*
- * Context switch.
- *
- * These is the CPU-specific parts of the context switcher cpu_switch()
- * These functions actually perform the TTB reload.
- *
- * NOTE: Special calling convention
- *	r1, r4-r13 must be preserved
- */
-ENTRY(arm7tdmi_context_switch)
-	b	_C_LABEL(arm7tdmi_setttb)
-END(arm7tdmi_context_switch)
-
diff --git a/sys/arm/arm/cpufunc_asm_arm8.S b/sys/arm/arm/cpufunc_asm_arm8.S
deleted file mode 100644
index 787e5b2..0000000
--- a/sys/arm/arm/cpufunc_asm_arm8.S
+++ /dev/null
@@ -1,296 +0,0 @@
-/*	$NetBSD: cpufunc_asm_arm8.S,v 1.2 2001/11/11 00:47:49 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 1997 ARM Limited
- * Copyright (c) 1997 Causality Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Causality Limited.
- * 4. The name of Causality Limited may not be used to endorse or promote
- *    products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * ARM8 assembly functions for CPU / MMU / TLB specific operations
- *
- */
-
-#include <machine/asm.h>
-__FBSDID("$FreeBSD$");
-
-ENTRY(arm8_clock_config)
-	mrc	p15, 0, r3, c15, c0, 0	/* Read the clock register */
-	bic	r2, r3, #0x11		/* turn off dynamic clocking
-					   and clear L bit */
-	mcr	p15, 0, r2, c15, c0, 0	/* Write clock register */
-
-	bic	r2, r3, r0		/* Clear bits */
-	eor	r2, r2, r1		/* XOR bits */
-	bic	r2, r2, #0x10		/* clear the L bit */
-
-	bic	r1, r2, #0x01		/* still keep dynamic clocking off */
-	mcr	p15, 0, r1, c15, c0, 0	/* Write clock register */
-	mov	r0, r0			/* NOP */
-	mov	r0, r0			/* NOP */
-	mov	r0, r0			/* NOP */
-	mov	r0, r0			/* NOP */
-	mcr	p15, 0, r2, c15, c0, 0 	/* Write clock register */
-	mov	r0, r3			/* Return old value */
-	RET
-END(arm8_clock_config)
-
-/*
- * Functions to set the MMU Translation Table Base register
- *
- * We need to clean and flush the cache as it uses virtual
- * addresses that are about to change.
- */
-ENTRY(arm8_setttb)
-	mrs	r3, cpsr
-	orr	r1, r3, #(I32_bit | F32_bit)
-	msr	cpsr_fsxc, r1
-
-	stmfd	sp!, {r0-r3, lr}
-	bl	_C_LABEL(arm8_cache_cleanID)
-	ldmfd	sp!, {r0-r3, lr}
-	mcr	p15, 0, r0, c7, c7, 0	/* flush I+D cache */
-
-	/* Write the TTB */
-	mcr	p15, 0, r0, c2, c0, 0
-
-	/* If we have updated the TTB we must flush the TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-
-	/* For good measure we will flush the IDC as well */
-	mcr	p15, 0, r0, c7, c7, 0
-
-	/* Make sure that pipeline is emptied */
-	mov	r0, r0
-	mov	r0, r0
-	msr	cpsr_fsxc, r3
-
-	RET
-END(arm8_setttb)
-
-/*
- * TLB functions
- */
-ENTRY(arm8_tlb_flushID)
-	mcr	p15, 0, r0, c8, c7, 0	/* flush I+D tlb */
-	RET
-END(arm8_tlb_flushID)
-
-ENTRY(arm8_tlb_flushID_SE)
-	mcr	p15, 0, r0, c8, c7, 1	/* flush I+D tlb single entry */
-	RET
-END(arm8_tlb_flushID_SE)
-
-/*
- * Cache functions
- */
-ENTRY(arm8_cache_flushID)
-	mcr	p15, 0, r0, c7, c7, 0	/* flush I+D cache */
-	RET
-END(arm8_cache_flushID)
-
-ENTRY(arm8_cache_flushID_E)
-	mcr	p15, 0, r0, c7, c7, 1	/* flush I+D single entry */
-	RET
-END(arm8_cache_flushID_E)
-
-ENTRY(arm8_cache_cleanID)
-	mov	r0, #0x00000000
-
-1:	mov	r2, r0
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-
-	adds	r0, r0, #0x04000000
-	bne	1b
-
-	RET
-END(arm8_cache_cleanID)
-
-ENTRY(arm8_cache_cleanID_E)
-	mcr	p15, 0, r0, c7, c11, 1	/* clean I+D single entry */
-	RET
-END(arm8_cache_cleanID_E)
-
-ENTRY(arm8_cache_purgeID)
-	/*
-	 * ARM810 bug 3
-	 *
-	 * Clean and invalidate entry will not invalidate the entry
-	 * if the line was already clean. (mcr p15, 0, rd, c7, 15, 1)
-	 *
-	 * Instead of using the clean and invalidate entry operation
-	 * use a separate clean and invalidate entry operations.
-	 * i.e.
-	 * mcr p15, 0, rd, c7, c11, 1
-	 * mcr p15, 0, rd, c7, c7, 1
-	 */
-
-	mov	r0, #0x00000000
-
-	mrs	r3, cpsr
-	orr	r2, r3, #(I32_bit | F32_bit)
-	msr	cpsr_fsxc, r2
-
-1:	mov	r2, r0
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-	add	r2, r2, #0x10
-	mcr	p15, 0, r2, c7, c11, 1
-	mcr	p15, 0, r2, c7, c7, 1
-
-	adds	r0, r0, #0x04000000
-	bne	1b
-
-	msr	cpsr_fsxc, r3
-	RET
-END(arm8_cache_purgeID)
-
-ENTRY(arm8_cache_purgeID_E)
-	/*
-	 * ARM810 bug 3
-	 *
-	 * Clean and invalidate entry will not invalidate the entry
-	 * if the line was already clean. (mcr p15, 0, rd, c7, 15, 1)
-	 *
-	 * Instead of using the clean and invalidate entry operation
-	 * use a separate clean and invalidate entry operations.
-	 * i.e.
-	 * mcr p15, 0, rd, c7, c11, 1
-	 * mcr p15, 0, rd, c7, c7, 1
-	 */
-	mrs	r3, cpsr
-	orr	r2, r3, #(I32_bit | F32_bit)
-	msr	cpsr_fsxc, r2
-	mcr	p15, 0, r0, c7, c11, 1	/* clean I+D single entry */
-	mcr	p15, 0, r0, c7, c7, 1	/* flush I+D single entry */
-	msr	cpsr_fsxc, r3
-	RET
-END(arm8_cache_purgeID_E)
-
-/*
- * Context switch.
- *
- * These is the CPU-specific parts of the context switcher cpu_switch()
- * These functions actually perform the TTB reload.
- *
- * NOTE: Special calling convention
- *	r1, r4-r13 must be preserved
- */
-ENTRY(arm8_context_switch)
-	/* For good measure we will flush the IDC as well */
-	mcr	p15, 0, r0, c7, c7, 0	/* flush I+D cache */
-
-	/* Write the TTB */
-	mcr	p15, 0, r0, c2, c0, 0
-
-	/* If we have updated the TTB we must flush the TLB */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush the I+D tlb */
-
-#if 0
-	/* For good measure we will flush the IDC as well */
-	mcr	p15, 0, r0, c7, c7, 0	/* flush I+D cache */
-#endif
-
-	/* Make sure that pipeline is emptied */
-	mov	r0, r0
-	mov	r0, r0
-	RET
-END(arm8_context_switch)
-
diff --git a/sys/arm/arm/cpufunc_asm_ixp12x0.S b/sys/arm/arm/cpufunc_asm_ixp12x0.S
deleted file mode 100644
index 481cf0d..0000000
--- a/sys/arm/arm/cpufunc_asm_ixp12x0.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/*	$NetBSD: cpufunc_asm_ixp12x0.S,v 1.2 2002/08/17 16:36:31 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <machine/asm.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * This function is the same as sa110_context_switch for now, the plan
- * is to make use of the process id register to avoid cache flushes.
- */
-ENTRY(ixp12x0_context_switch)
-	/*
-	 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
-	 * Thus the data cache will contain only kernel data and the
-	 * instruction cache will contain only kernel code, and all
-	 * kernel mappings are shared by all processes.
-	 */
-
-	/* Write the TTB */
-	mcr	p15, 0, r0, c2, c0, 0
-
-	/* If we have updated the TTB we must flush the TLB */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush the I+D tlb */
-
-	/* Make sure that pipeline is emptied */
-	mov	r0, r0
-	mov	r0, r0
-	RET
-END(ixp12x0_context_switch)
-
-ENTRY(ixp12x0_drain_readbuf)
-	mcr	p15, 0, r0, c9, c0, 0		/* drain read buffer */
-	RET
-END(ixp12x0_drain_readbuf)
-
-/*
- * Information for the IXP12X0 cache clean/purge functions:
- *
- *      * Virtual address of the memory region to use
- *      * Size of memory region
- */
-	.data
-
-	.global _C_LABEL(ixp12x0_cache_clean_addr)
-_C_LABEL(ixp12x0_cache_clean_addr):
-        .word   0xf0000000
-
-	.global _C_LABEL(ixp12x0_cache_clean_size)
-_C_LABEL(ixp12x0_cache_clean_size):
-	.word   0x00008000
-
-	.text
-
-.Lixp12x0_cache_clean_addr:
-	.word   _C_LABEL(ixp12x0_cache_clean_addr)
-.Lixp12x0_cache_clean_size:
-	.word   _C_LABEL(ixp12x0_cache_clean_size)
diff --git a/sys/arm/arm/cpufunc_asm_sa1.S b/sys/arm/arm/cpufunc_asm_sa1.S
deleted file mode 100644
index 77602b1..0000000
--- a/sys/arm/arm/cpufunc_asm_sa1.S
+++ /dev/null
@@ -1,337 +0,0 @@
-/*	$NetBSD: cpufunc_asm_sa1.S,v 1.8 2002/08/17 16:36:32 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 1997,1998 Mark Brinicombe.
- * Copyright (c) 1997 Causality Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Causality Limited.
- * 4. The name of Causality Limited may not be used to endorse or promote
- *    products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * SA-1 assembly functions for CPU / MMU / TLB specific operations
- *
- */
-
-#include <machine/asm.h>
-__FBSDID("$FreeBSD$");
-
-.Lblock_userspace_access:
-	.word	_C_LABEL(block_userspace_access)
-
-/*
- * Functions to set the MMU Translation Table Base register
- *
- * We need to clean and flush the cache as it uses virtual
- * addresses that are about to change.
- */
-ENTRY(getttb)
-	mrc	p15, 0, r0, c2, c0, 0
-ENTRY(sa1_setttb)
-#ifdef CACHE_CLEAN_BLOCK_INTR
-	mrs	r3, cpsr
-	orr	r1, r3, #(I32_bit | F32_bit)
-	msr	cpsr_fsxc, r1
-#else
-	ldr	r3, .Lblock_userspace_access
-	ldr	r2, [r3]
-	orr	r1, r2, #1
-	str	r1, [r3]
-#endif
-	stmfd	sp!, {r0-r3, lr}
-	bl	_C_LABEL(sa1_cache_cleanID)
-	ldmfd	sp!, {r0-r3, lr}
-	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I$ and BTB */
-	mcr	p15, 0, r0, c7, c10, 4	/* drain write and fill buffer */
-
-	/* Write the TTB */
-	mcr	p15, 0, r0, c2, c0, 0
-
-	/* If we have updated the TTB we must flush the TLB */
-	mcr	p15, 0, r0, c8, c7, 0	/* invalidate I+D TLB */
-
-	/* The cleanID above means we only need to flush the I cache here */
-	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I$ and BTB */
-
-	/* Make sure that pipeline is emptied */
-	mov	r0, r0
-	mov	r0, r0
-#ifdef CACHE_CLEAN_BLOCK_INTR
-	msr	cpsr_fsxc, r3
-#else
-	str	r2, [r3]
-#endif
-	RET
-END(getttb)
-END(sa1_setttb)
-
-/*
- * TLB functions
- */
-ENTRY(sa1_tlb_flushID_SE)
-	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
-	mcr	p15, 0, r0, c8, c5, 0	/* flush I tlb */
-	RET
-END(sa1_tlb_flushID_SE)
-
-/*
- * Cache functions
- */
-ENTRY(sa1_cache_flushID)
-	mcr	p15, 0, r0, c7, c7, 0	/* flush I+D cache */
-	RET
-END(sa1_cache_flushID)
-
-ENTRY(sa1_cache_flushI)
-	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache */
-	RET
-END(sa1_cache_flushI)
-
-ENTRY(sa1_cache_flushD)
-	mcr	p15, 0, r0, c7, c6, 0	/* flush D cache */
-	RET
-END(sa1_cache_flushD)
-
-ENTRY(sa1_cache_flushD_SE)
-	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
-	RET
-END(sa1_cache_flushD_SE)
-
-ENTRY(sa1_cache_cleanD_E)
-	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
-	RET
-END(sa1_cache_cleanD_E)
-
-/*
- * Information for the SA-1 cache clean/purge functions:
- *
- *	* Virtual address of the memory region to use
- *	* Size of memory region
- */
-	.data
-
-	.global	_C_LABEL(sa1_cache_clean_addr)
-_C_LABEL(sa1_cache_clean_addr):
-	.word	0xf0000000
-
-	.global	_C_LABEL(sa1_cache_clean_size)
-_C_LABEL(sa1_cache_clean_size):
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-	.word	0x00004000
-#else
-	.word	0x00008000
-#endif
-
-	.text
-
-.Lsa1_cache_clean_addr:
-	.word	_C_LABEL(sa1_cache_clean_addr)
-.Lsa1_cache_clean_size:
-	.word	_C_LABEL(sa1_cache_clean_size)
-
-#ifdef CACHE_CLEAN_BLOCK_INTR
-#define	SA1_CACHE_CLEAN_BLOCK						\
-	mrs	r3, cpsr					;	\
-	orr	r0, r3, #(I32_bit | F32_bit)			;	\
-	msr	cpsr_fsxc, r0
-
-#define	SA1_CACHE_CLEAN_UNBLOCK						\
-	msr	cpsr_fsxc, r3
-#else
-#define	SA1_CACHE_CLEAN_BLOCK						\
-	ldr	r3, .Lblock_userspace_access			;	\
-	ldr	ip, [r3]					;	\
-	orr	r0, ip, #1					;	\
-	str	r0, [r3]
-
-#define	SA1_CACHE_CLEAN_UNBLOCK						\
-	str	ip, [r3]
-#endif /* CACHE_CLEAN_BLOCK_INTR */
-
-#ifdef DOUBLE_CACHE_CLEAN_BANK
-#define	SA1_DOUBLE_CACHE_CLEAN_BANK					\
-	eor	r0, r0, r1					;	\
-	str	r0, [r2]
-#else
-#define	SA1_DOUBLE_CACHE_CLEAN_BANK	/* nothing */
-#endif /* DOUBLE_CACHE_CLEAN_BANK */
-
-#define	SA1_CACHE_CLEAN_PROLOGUE					\
-	SA1_CACHE_CLEAN_BLOCK					;	\
-	ldr	r2, .Lsa1_cache_clean_addr			;	\
-	ldmia	r2, {r0, r1}					;	\
-	SA1_DOUBLE_CACHE_CLEAN_BANK
-
-#define	SA1_CACHE_CLEAN_EPILOGUE					\
-	SA1_CACHE_CLEAN_UNBLOCK
-
-ENTRY_NP(sa1_cache_syncI)
-ENTRY_NP(sa1_cache_purgeID)
-	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache (D cleaned below) */
-ENTRY_NP(sa1_cache_cleanID)
-ENTRY_NP(sa1_cache_purgeD)
-ENTRY(sa1_cache_cleanD)
-	SA1_CACHE_CLEAN_PROLOGUE
-
-1:	ldr	r2, [r0], #32
-	subs	r1, r1, #32
-	bne	1b
-
-	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
-
-	SA1_CACHE_CLEAN_EPILOGUE
-	RET
-END(sa1_cache_syncI)
-END(sa1_cache_purgeID)
-END(sa1_cache_cleanID)
-END(sa1_cache_purgeD)
-END(sa1_cache_cleanD)
-
-ENTRY(sa1_cache_purgeID_E)
-	mcr	p15, 0, r0, c7, c10, 1	/* clean dcache entry */
-	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
-	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache */
-	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
-	RET
-END(sa1_cache_purgeID_E)
-
-ENTRY(sa1_cache_purgeD_E)
-	mcr	p15, 0, r0, c7, c10, 1	/* clean dcache entry */
-	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
-	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
-	RET
-END(sa1_cache_purgeD_E)
-
-/*
- * Soft functions
- */
-/* sa1_cache_syncI is identical to sa1_cache_purgeID */
-
-ENTRY(sa1_cache_cleanID_rng)
-ENTRY(sa1_cache_cleanD_rng)
-	cmp	r1, #0x4000
-	bcs	_C_LABEL(sa1_cache_cleanID)
-
-	and	r2, r0, #0x1f
-	add	r1, r1, r2
-	bic	r0, r0, #0x1f
-
-1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
-	add	r0, r0, #32
-	subs	r1, r1, #32
-	bhi	1b
-
-	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
-	RET
-END(sa1_cache_cleanID_rng)
-END(sa1_cache_cleanD_rng)
-
-ENTRY(sa1_cache_purgeID_rng)
-	cmp	r1, #0x4000
-	bcs	_C_LABEL(sa1_cache_purgeID)
-
-	and	r2, r0, #0x1f
-	add	r1, r1, r2
-	bic	r0, r0, #0x1f
-
-1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
-	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
-	add	r0, r0, #32
-	subs	r1, r1, #32
-	bhi	1b
-
-	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
-	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache */
-	RET
-END(sa1_cache_purgeID_rng)
-
-ENTRY(sa1_cache_purgeD_rng)
-	cmp	r1, #0x4000
-	bcs	_C_LABEL(sa1_cache_purgeD)
-
-	and	r2, r0, #0x1f
-	add	r1, r1, r2
-	bic	r0, r0, #0x1f
-
-1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
-	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
-	add	r0, r0, #32
-	subs	r1, r1, #32
-	bhi	1b
-
-	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
-	RET
-END(sa1_cache_purgeD_rng)
-
-ENTRY(sa1_cache_syncI_rng)
-	cmp	r1, #0x4000
-	bcs	_C_LABEL(sa1_cache_syncI)
-
-	and	r2, r0, #0x1f
-	add	r1, r1, r2
-	bic	r0, r0, #0x1f
-
-1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
-	add	r0, r0, #32
-	subs	r1, r1, #32
-	bhi	1b
-
-	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
-	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache */
-
-	RET
-END(sa1_cache_syncI_rng)
-
-/*
- * Context switch.
- *
- * These is the CPU-specific parts of the context switcher cpu_switch()
- * These functions actually perform the TTB reload.
- *
- * NOTE: Special calling convention
- *	r1, r4-r13 must be preserved
- */
-#if defined(CPU_SA110)
-ENTRY(sa110_context_switch)
-	/*
-	 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
-	 * Thus the data cache will contain only kernel data and the
-	 * instruction cache will contain only kernel code, and all
-	 * kernel mappings are shared by all processes.
-	 */
-
-	/* Write the TTB */
-	mcr	p15, 0, r0, c2, c0, 0
-
-	/* If we have updated the TTB we must flush the TLB */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush the I+D tlb */
-
-	/* Make sure that pipeline is emptied */
-	mov	r0, r0
-	mov	r0, r0
-	RET
-END(sa110_context_switch)
-#endif
diff --git a/sys/arm/arm/cpufunc_asm_sa11x0.S b/sys/arm/arm/cpufunc_asm_sa11x0.S
deleted file mode 100644
index ffd214e..0000000
--- a/sys/arm/arm/cpufunc_asm_sa11x0.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/*	$NetBSD: cpufunc_asm_sa11x0.S,v 1.3 2002/08/17 16:36:32 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <machine/asm.h>
-__FBSDID("$FreeBSD$");
-
-	.data
-	.global	_C_LABEL(sa11x0_idle_mem)
-_C_LABEL(sa11x0_idle_mem):
-	.word	0
-
-	.text
-
-	.align	5
-
-	/* We're now 32-byte aligned */
-
-.Lsa11x0_idle_mem:
-	.word	_C_LABEL(sa11x0_idle_mem)				/* 1 */
-
-/*
- * sa11x0_cpusleep
- *
- * This is called when there is nothing on any of the run queues.
- * We go into IDLE mode so that any IRQ or FIQ will awaken us.
- */
-ENTRY(sa11x0_cpu_sleep)
-	ldr	r1, .Lsa11x0_idle_mem	/* get address of... */		/* 2 */
-	nop								/* 3 */
-	ldr	r1, [r1]		/* ...non-cacheable page */	/* 4 */
-	nop								/* 5 */
-
-	/*
-	 * SA-1110 manual, 9.5.2.1 (Entering Idle Mode) says that
-	 * to enter idle mode:
-	 *
-	 *	* Disable clock switching
-	 *	* Issue load from non-cacheable address
-	 *	* Issue "wait for interrupt"
-	 *
-	 * The 3-insn sequence must reside in the first 3 words
-	 * of a cache line.
-	 *
-	 * We must disable interrupts in the CPSR so that we can
-	 * re-enable clock switching before servicing interrupts.
-	 */
-
-	mrs	r3, cpsr						/* 6 */
-	orr	r2, r3, #(I32_bit|F32_bit)				/* 7 */
-	msr	cpsr_fsxc, r2						/* 8 */
-
-	/* We're now 32-byte aligned */
-
-	mcr	p15, 0, r0, c15, c2, 2	/* disable clock switching */
-	ldr	r0, [r1]		/* load from non-cacheable address */
-	mcr	p15, 0, r0, c15, c8, 2	/* wait for interrupt */
-
-	mcr	p15, 0, r0, c15, c1, 2	/* re-enable clock switching */
-
-	/* Restore interrupts (which will cause them to be serviced). */
-	msr	cpsr_fsxc, r3
-	RET
-END(sa11x0_cpu_sleep)
-
-/*
- * This function is the same as sa110_context_switch for now, the plan
- * is to make use of the process id register to avoid cache flushes.
- */
-ENTRY(sa11x0_context_switch)
-	/*
-	 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
-	 * Thus the data cache will contain only kernel data and the
-	 * instruction cache will contain only kernel code, and all
-	 * kernel mappings are shared by all processes.
-	 */
-
-	/* Write the TTB */
-	mcr	p15, 0, r0, c2, c0, 0
-
-	/* If we have updated the TTB we must flush the TLB */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush the I+D tlb */
-
-	/* Make sure that pipeline is emptied */
-	mov	r0, r0
-	mov	r0, r0
-	RET
-END(sa11x0_context_switch)
-
-ENTRY(sa11x0_drain_readbuf)
-	mcr	p15, 0, r0, c9, c0, 0		/* drain read buffer */
-	RET
-END(sa11x0_drain_readbuf)
-
diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c
index 9371a6d..559b992 100644
--- a/sys/arm/arm/elf_trampoline.c
+++ b/sys/arm/arm/elf_trampoline.c
@@ -56,13 +56,7 @@ extern void do_call(void *, void *, void *, int);
 
 #define GZ_HEAD	0xa
 
-#ifdef CPU_ARM7TDMI
-#define cpu_idcache_wbinv_all	arm7tdmi_cache_flushID
-extern void arm7tdmi_cache_flushID(void);
-#elif defined(CPU_ARM8)
-#define cpu_idcache_wbinv_all	arm8_cache_purgeID
-extern void arm8_cache_purgeID(void);
-#elif defined(CPU_ARM9)
+#if defined(CPU_ARM9)
 #define cpu_idcache_wbinv_all	arm9_idcache_wbinv_all
 extern void arm9_idcache_wbinv_all(void);
 #elif defined(CPU_FA526) || defined(CPU_FA626TE)
@@ -76,10 +70,6 @@ extern void armv5_ec_idcache_wbinv_all(void);
 extern void arm10_idcache_wbinv_all(void);
 #elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
 #define cpu_idcache_wbinv_all	armv6_idcache_wbinv_all
-#elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \
-    defined(CPU_IXP12X0)
-#define cpu_idcache_wbinv_all	sa1_cache_purgeID
-extern void sa1_cache_purgeID(void);
 #elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
   defined(CPU_XSCALE_80219)
diff --git a/sys/arm/arm/exception.S b/sys/arm/arm/exception.S
index d7ef5f2..d49e20d 100644
--- a/sys/arm/arm/exception.S
+++ b/sys/arm/arm/exception.S
@@ -56,187 +56,408 @@ __FBSDID("$FreeBSD$");
 	.text	
 	.align	0
 
-AST_LOCALS
+/*
+ * ASM macros for pushing and pulling trapframes from the stack
+ *
+ * These macros are used to handle the irqframe and trapframe structures
+ * defined above.
+ */
 
 /*
- * reset_entry:
+ * PUSHFRAME - macro to push a trap frame on the stack in the current mode
+ * Since the current mode is used, the SVC lr field is not defined.
  *
- *	Handler for Reset exception.
+ * NOTE: r13 and r14 are stored separately as a work around for the
+ * SA110 rev 2 STM^ bug
  */
-ASENTRY_NP(reset_entry)
-	adr	r0, Lreset_panicmsg
-	bl	_C_LABEL(panic)
-	/* NOTREACHED */
-Lreset_panicmsg:
-	.asciz	"Reset vector called, LR = 0x%08x"
-	.balign	4
-END(reset_entry)
+#ifdef ARM_TP_ADDRESS
+#define PUSHFRAME							   \
+	sub	sp, sp, #4;		/* Align the stack */		   \
+	str	lr, [sp, #-4]!;		/* Push the return address */	   \
+	sub	sp, sp, #(4*17);	/* Adjust the stack pointer */	   \
+	stmia	sp, {r0-r12};		/* Push the user mode registers */ \
+	add	r0, sp, #(4*13);	/* Adjust the stack pointer */	   \
+	stmia	r0, {r13-r14}^;		/* Push the user mode registers */ \
+	mov	r0, r0;			/* NOP for previous instruction */ \
+	mrs	r0, spsr;		/* Put the SPSR on the stack */	   \
+	str	r0, [sp, #-4]!;						   \
+	ldr	r0, =ARM_RAS_START;					   \
+	mov	r1, #0;							   \
+	str	r1, [r0];						   \
+	mov	r1, #0xffffffff;					   \
+	str	r1, [r0, #4];
+#else
+#define PUSHFRAME							   \
+	sub	sp, sp, #4;		/* Align the stack */		   \
+	str	lr, [sp, #-4]!;		/* Push the return address */	   \
+	sub	sp, sp, #(4*17);	/* Adjust the stack pointer */	   \
+	stmia	sp, {r0-r12};		/* Push the user mode registers */ \
+	add	r0, sp, #(4*13);	/* Adjust the stack pointer */	   \
+	stmia	r0, {r13-r14}^;		/* Push the user mode registers */ \
+	mov	r0, r0;			/* NOP for previous instruction */ \
+	mrs	r0, spsr;		/* Put the SPSR on the stack */	   \
+	str	r0, [sp, #-4]!;
+#endif
 
 /*
- * swi_entry
+ * PULLFRAME - macro to pull a trap frame from the stack in the current mode
+ * Since the current mode is used, the SVC lr field is ignored.
+ */
+
+#ifdef ARM_TP_ADDRESS
+#define PULLFRAME							   \
+	ldr	r0, [sp], #4;		/* Get the SPSR from stack */	   \
+	msr	spsr_fsxc, r0;						   \
+	ldmia	sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
+	mov	r0, r0;			/* NOP for previous instruction */ \
+	add	sp, sp, #(4*17);	/* Adjust the stack pointer */	   \
+ 	ldr	lr, [sp], #4;		/* Pull the return address */	   \
+	add	sp, sp, #4		/* Align the stack */
+#else 
+#define PULLFRAME							   \
+	ldr	r0, [sp], #4	;	/* Get the SPSR from stack */	   \
+	msr	spsr_fsxc, r0;						   \
+	clrex;								   \
+	ldmia   sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
+	mov	r0, r0;			/* NOP for previous instruction */ \
+	add	sp, sp, #(4*17);	/* Adjust the stack pointer */	   \
+ 	ldr	lr, [sp], #4;		/* Pull the return address */	   \
+	add	sp, sp, #4		/* Align the stack */
+#endif
+
+/*
+ * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
+ * This should only be used if the processor is not currently in SVC32
+ * mode. The processor mode is switched to SVC mode and the trap frame is
+ * stored. The SVC lr field is used to store the previous value of
+ * lr in SVC mode.
  *
- *	Handler for the Software Interrupt exception.
+ * NOTE: r13 and r14 are stored separately as a work around for the
+ * SA110 rev 2 STM^ bug
  */
-ASENTRY_NP(swi_entry)
-	STOP_UNWINDING			/* Don't unwind past here */
+#ifdef ARM_TP_ADDRESS
+#define PUSHFRAMEINSVC							   \
+	stmdb	sp, {r0-r3};		/* Save 4 registers */		   \
+	mov	r0, lr;			/* Save xxx32 r14 */		   \
+	mov	r1, sp;			/* Save xxx32 sp */		   \
+	mrs	r3, spsr;		/* Save xxx32 spsr */		   \
+	mrs	r2, cpsr; 		/* Get the CPSR */		   \
+	bic	r2, r2, #(PSR_MODE);	/* Fix for SVC mode */		   \
+	orr	r2, r2, #(PSR_SVC32_MODE);				   \
+	msr	cpsr_c, r2;		/* Punch into SVC mode */	   \
+	mov	r2, sp;			/* Save	SVC sp */		   \
+	bic	sp, sp, #7;		/* Align sp to an 8-byte addrress */  \
+	sub	sp, sp, #4;		/* Pad trapframe to keep alignment */ \
+	str	r0, [sp, #-4]!;		/* Push return address */	   \
+	str	lr, [sp, #-4]!;		/* Push SVC lr */		   \
+	str	r2, [sp, #-4]!;		/* Push SVC sp */		   \
+	msr	spsr_fsxc, r3;		/* Restore correct spsr */	   \
+	ldmdb	r1, {r0-r3};		/* Restore 4 regs from xxx mode */ \
+	sub	sp, sp, #(4*15);	/* Adjust the stack pointer */	   \
+	stmia	sp, {r0-r12};		/* Push the user mode registers */ \
+	add	r0, sp, #(4*13);	/* Adjust the stack pointer */	   \
+	stmia	r0, {r13-r14}^;		/* Push the user mode registers */ \
+	mov	r0, r0;			/* NOP for previous instruction */ \
+	ldr	r5, =ARM_RAS_START;	/* Check if there's any RAS */	   \
+	ldr	r4, [r5, #4];		/* reset it to point at the     */ \
+	cmp	r4, #0xffffffff;	/* end of memory if necessary;  */ \
+	movne	r1, #0xffffffff;	/* leave value in r4 for later  */ \
+	strne	r1, [r5, #4];		/* comparision against PC.      */ \
+	ldr	r3, [r5];		/* Retrieve global RAS_START    */ \
+	cmp	r3, #0;			/* and reset it if non-zero.    */ \
+	movne	r1, #0;			/* If non-zero RAS_START and    */ \
+	strne	r1, [r5];		/* PC was lower than RAS_END,   */ \
+	ldrne	r1, [r0, #16];		/* adjust the saved PC so that  */ \
+	cmpne	r4, r1;			/* execution later resumes at   */ \
+	strhi	r3, [r0, #16];		/* the RAS_START location.      */ \
+	mrs	r0, spsr;						   \
+	str	r0, [sp, #-4]!
+#else
+#define PUSHFRAMEINSVC							   \
+	stmdb	sp, {r0-r3};		/* Save 4 registers */		   \
+	mov	r0, lr;			/* Save xxx32 r14 */		   \
+	mov	r1, sp;			/* Save xxx32 sp */		   \
+	mrs	r3, spsr;		/* Save xxx32 spsr */		   \
+	mrs	r2, cpsr;		/* Get the CPSR */		   \
+	bic	r2, r2, #(PSR_MODE);	/* Fix for SVC mode */		   \
+	orr	r2, r2, #(PSR_SVC32_MODE);				   \
+	msr	cpsr_c, r2;		/* Punch into SVC mode */	   \
+	mov	r2, sp;			/* Save	SVC sp */		   \
+	bic	sp, sp, #7;		/* Align sp to an 8-byte addrress */  \
+	sub	sp, sp, #4;		/* Pad trapframe to keep alignment */ \
+	str	r0, [sp, #-4]!;		/* Push return address */	   \
+	str	lr, [sp, #-4]!;		/* Push SVC lr */		   \
+	str	r2, [sp, #-4]!;		/* Push SVC sp */		   \
+	msr	spsr_fsxc, r3;		/* Restore correct spsr */	   \
+	ldmdb	r1, {r0-r3};		/* Restore 4 regs from xxx mode */ \
+	sub	sp, sp, #(4*15);	/* Adjust the stack pointer */	   \
+	stmia	sp, {r0-r12};		/* Push the user mode registers */ \
+	add	r0, sp, #(4*13);	/* Adjust the stack pointer */	   \
+	stmia	r0, {r13-r14}^;		/* Push the user mode registers */ \
+	mov	r0, r0;			/* NOP for previous instruction */ \
+	mrs	r0, spsr;		/* Put the SPSR on the stack */	   \
+	str	r0, [sp, #-4]!
+#endif
 
-	PUSHFRAME
+/*
+ * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
+ * in SVC32 mode and restore the saved processor mode and PC.
+ * This should be used when the SVC lr register needs to be restored on
+ * exit.
+ */
 
-	mov	r0, sp			/* Pass the frame to any function */
-	bl	_C_LABEL(swi_handler)	/* It's a SWI ! */
+#ifdef ARM_TP_ADDRESS
+#define PULLFRAMEFROMSVCANDEXIT						   \
+	ldr	r0, [sp], #4;		/* Get the SPSR from stack */	   \
+	msr	spsr_fsxc, r0;		/* restore SPSR */		   \
+	ldmia	sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
+	mov	r0, r0;	  		/* NOP for previous instruction */ \
+	add	sp, sp, #(4*15);	/* Adjust the stack pointer */	   \
+	ldmia	sp, {sp, lr, pc}^	/* Restore lr and exit */
+#else 
+#define PULLFRAMEFROMSVCANDEXIT						   \
+	ldr	r0, [sp], #4;		/* Get the SPSR from stack */	   \
+	msr	spsr_fsxc, r0;		/* restore SPSR */		   \
+	clrex;								   \
+	ldmia	sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
+	mov	r0, r0;	  		/* NOP for previous instruction */ \
+	add	sp, sp, #(4*15);	/* Adjust the stack pointer */	   \
+	ldmia	sp, {sp, lr, pc}^	/* Restore lr and exit */
+#endif
 
-	DO_AST
-	PULLFRAME
-	movs	pc, lr			/* Exit */
+#if defined(__ARM_EABI__)
+/*
+ * Unwind hints so we can unwind past functions that use
+ * PULLFRAMEFROMSVCANDEXIT. They are run in reverse order.
+ * As the last thing we do is restore the stack pointer
+ * we can ignore the padding at the end of struct trapframe.
+ */
+#define	UNWINDSVCFRAME							   \
+	.save {r13-r15};		/* Restore sp, lr, pc */	   \
+	.pad #(2*4);			/* Skip user sp and lr */	   \
+	.save {r0-r12};			/* Restore r0-r12 */		   \
+	.pad #(4)			/* Skip spsr */
+#else
+#define	UNWINDSVCFRAME
+#endif
+
+#define	DO_AST								\
+	ldr	r0, [sp]		/* Get the SPSR from stack */	;\
+	mrs	r4, cpsr		/* save CPSR */			;\
+	orr	r1, r4, #(I32_bit|F32_bit)				;\
+	msr	cpsr_c, r1		/* Disable interrupts */	;\
+	and	r0, r0, #(PSR_MODE)	/* Returning to USR mode? */	;\
+	teq	r0, #(PSR_USR32_MODE)					;\
+	bne	2f			/* Nope, get out now */		;\
+	bic	r4, r4, #(I32_bit|F32_bit)				;\
+1:	GET_CURTHREAD_PTR(r5)						;\
+	ldr	r1, [r5, #(TD_FLAGS)]					;\
+	and	r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED)		;\
+	teq	r1, #0x00000000						;\
+	beq	2f			/* Nope. Just bail */		;\
+	msr	cpsr_c, r4		/* Restore interrupts */	;\
+	mov	r0, sp							;\
+	bl	_C_LABEL(ast)		/* ast(frame) */		;\
+	orr	r0, r4, #(I32_bit|F32_bit)				;\
+	msr	cpsr_c, r0						;\
+	b	1b							;\
+2:
+
+
+/*
+ * Entry point for a Software Interrupt (SWI).
+ *
+ * The hardware switches to svc32 mode on a swi, so we're already on the
+ * right stack; just build a trapframe and call the handler.
+ */
+ASENTRY_NP(swi_entry)
+	PUSHFRAME			/* Build the trapframe on the */
+	mov	r0, sp			/* scv32 stack, pass it to the */
+	bl	_C_LABEL(swi_handler)	/* swi handler. */
+	/*
+	 * The fork_trampoline() code in swtch.S aranges for the MI fork_exit()
+	 * to return to swi_exit here, to return to userland.  The net effect is
+	 * that a newly created thread appears to return from a SWI just like
+	 * the parent thread that created it.
+	 */
+ASENTRY_NP(swi_exit)
+	DO_AST				/* Handle pending signals. */
+	PULLFRAME			/* Deallocate trapframe. */
+	movs	pc, lr			/* Return to userland. */
+	STOP_UNWINDING			/* Don't unwind into user mode. */
+END(swi_exit)
 END(swi_entry)
 
 /*
- * prefetch_abort_entry:
+ * Standard exception exit handler.
  *
- *	Handler for the Prefetch Abort exception.
+ * This is used to return from all exceptions except SWI.  It uses DO_AST and
+ * PULLFRAMEFROMSVCANDEXIT and can only be called if the exception entry code
+ * used PUSHFRAMEINSVC.
+ *
+ * If the return is to user mode, this uses DO_AST to deliver any pending
+ * signals and/or handle TDF_NEEDRESCHED first.
+ */
+ASENTRY_NP(exception_exit)
+	DO_AST				/* Handle pending signals. */
+	PULLFRAMEFROMSVCANDEXIT		/* Return. */
+	UNWINDSVCFRAME			/* Special unwinding for exceptions. */
+END(exception_exit)
+
+/*
+ * Entry point for a Prefetch Abort exception.
+ *
+ * The hardware switches to the abort mode stack; we switch to svc32 before
+ * calling the handler, then return directly to the original mode/stack 
+ * on exit (without transitioning back through the abort mode stack).
  */
 ASENTRY_NP(prefetch_abort_entry)
 #ifdef __XSCALE__
 	nop				/* Make absolutely sure any pending */
 	nop				/* imprecise aborts have occurred. */
 #endif
-        sub     lr, lr, #0x00000004     /* Adjust the lr */
-
-	PUSHFRAMEINSVC
-	ldr	r1, Lprefetch_abort_handler_address
-	adr	lr, exception_exit
- 	mov	r0, sp			/* pass the stack pointer as r0 */
-	ldr	pc, [r1]
-
-Lprefetch_abort_handler_address:
-	.word	_C_LABEL(prefetch_abort_handler_address)
-
-	.data
-	.global	_C_LABEL(prefetch_abort_handler_address)
-
-_C_LABEL(prefetch_abort_handler_address):
-	.word	abortprefetch
-
-	.text
-abortprefetch:
-        adr     r0, abortprefetchmsg
-	b	_C_LABEL(panic)
-
-abortprefetchmsg:
-        .asciz  "abortprefetch"
-        .align  0
+	sub	lr, lr, #4		/* Adjust the lr. Transition to scv32 */
+	PUSHFRAMEINSVC			/* mode stack, build trapframe there. */
+	adr	lr, exception_exit	/* Return from handler via standard */
+	mov	r0, sp			/* exception exit routine.  Pass the */
+	b	prefetch_abort_handler	/* trapframe to the handler. */
 END(prefetch_abort_entry)
 
 /*
- * data_abort_entry:
+ * Entry point for a Data Abort exception.
  *
- *	Handler for the Data Abort exception.
+ * The hardware switches to the abort mode stack; we switch to svc32 before
+ * calling the handler, then return directly to the original mode/stack 
+ * on exit (without transitioning back through the abort mode stack).
  */
 ASENTRY_NP(data_abort_entry)
 #ifdef __XSCALE__
 	nop				/* Make absolutely sure any pending */
 	nop				/* imprecise aborts have occurred. */
 #endif
-
-        sub     lr, lr, #0x00000008     /* Adjust the lr */
-	PUSHFRAMEINSVC			/* Push trap frame and switch */
-					/* to SVC32 mode */
-	ldr	r1, Ldata_abort_handler_address
-	adr	lr, exception_exit
-	mov	r0, sp			/* pass the stack pointer as r0 */
-	ldr	pc, [r1]
-Ldata_abort_handler_address:
-	.word	_C_LABEL(data_abort_handler_address)
-
-	.data
-	.global	_C_LABEL(data_abort_handler_address)
-_C_LABEL(data_abort_handler_address):
-	.word	abortdata
-
-	.text
-abortdata:
-        adr     r0, abortdatamsg
-	b	_C_LABEL(panic)
-
-abortdatamsg:
-        .asciz  "abortdata"
-        .align  0
+	sub	lr, lr, #8		/* Adjust the lr. Transition to scv32 */
+	PUSHFRAMEINSVC			/* mode stack, build trapframe there. */
+	adr	lr, exception_exit	/* Return from handler via standard */
+	mov	r0, sp			/* exception exit routine.  Pass the */
+	b	data_abort_handler	/* trapframe to the handler. */
 END(data_abort_entry)
 
 /*
- * address_exception_entry:
+ * Entry point for an Undefined Instruction exception.
  *
- *	Handler for the Address Exception exception.
+ * The hardware switches to the undefined mode stack; we switch to svc32 before
+ * calling the handler, then return directly to the original mode/stack 
+ * on exit (without transitioning back through the undefined mode stack).
+ */
+ASENTRY_NP(undefined_entry)
+	sub	lr, lr, #4		/* Adjust the lr. Transition to scv32 */
+	PUSHFRAMEINSVC			/* mode stack, build trapframe there. */
+	adr	lr, exception_exit      /* Return from handler via standard */
+	mov	r0, sp			/* exception exit routine.  Pass the */
+	b	undefinedinstruction	/* trapframe to the handler. */
+END(undefined_entry)
+
+/*
+ * Entry point for a normal IRQ.
  *
- *	NOTE: This exception isn't really used on arm32.  We
- *	print a warning message to the console and then treat
- *	it like a Data Abort.
+ * The hardware switches to the IRQ mode stack; we switch to svc32 before
+ * calling the handler, then return directly to the original mode/stack 
+ * on exit (without transitioning back through the IRQ mode stack).
  */
-ASENTRY_NP(address_exception_entry)
-	mrs	r1, cpsr
-	mrs	r2, spsr
+ASENTRY_NP(irq_entry)
+	sub	lr, lr, #4		/* Adjust the lr. Transition to scv32 */
+	PUSHFRAMEINSVC			/* mode stack, build trapframe there. */
+	adr	lr, exception_exit	/* Return from handler via standard */
+	mov	r0, sp			/* exception exit routine.  Pass the */
+	b	_C_LABEL(arm_irq_handler)/* trapframe to the handler. */
+END(irq_entry)                           
+
+/*
+ * Entry point for an FIQ interrupt.
+ *
+ * We don't currently support FIQ handlers very much.  Something can 
+ * install itself in the FIQ vector using code (that may or may not work
+ * these days) in fiq.c.  If nobody does that and an FIQ happens, this
+ * default handler just disables FIQs and otherwise ignores it.
+ */
+ASENTRY_NP(fiq_entry)
+	mrs	r8, cpsr		/* FIQ handling isn't supported, */
+	bic	r8, #(F32_bit)		/* just disable FIQ and return.  */
+	msr	cpsr_c, r8		/* The r8 we trash here is the  */
+	subs	pc, lr, #4		/* banked FIQ-mode r8. */
+END(fiq_entry)
+
+/*
+ * Entry point for an Address Exception exception.
+ * This is an arm26 exception that should never happen.
+ */
+ASENTRY_NP(addr_exception_entry)
 	mov	r3, lr
-	adr	r0, Laddress_exception_msg
-	bl	_C_LABEL(printf)	/* XXX CLOBBERS LR!! */
-	b	data_abort_entry
-Laddress_exception_msg:
+	mrs	r2, spsr
+	mrs	r1, cpsr
+	adr	r0, Laddr_exception_msg
+	b	_C_LABEL(panic)
+Laddr_exception_msg:
 	.asciz	"Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n"
 	.balign	4
-END(address_exception_entry)
+END(addr_exception_entry)
 
 /*
- * General exception exit handler
- * (Placed here to be within range of all the references to it)
- *
- * It exits straight away if not returning to USR mode.
- * This loops around delivering any pending ASTs.
- * Interrupts are disabled at suitable points to avoid ASTs
- * being posted between testing and exit to user mode.
- *
- * This function uses PULLFRAMEFROMSVCANDEXIT and DO_AST and can
- * only be called if the exception handler used PUSHFRAMEINSVC.
- *
- * For EABI, don't try to unwind any further than this.  This is a
- * stopgap measure to avoid getting stuck in a loop in the unwinder,
- * which happens because we don't yet provide the proper unwind info
- * here that describes which registers are being restored.
+ * Entry point for the system Reset vector.  
+ * This should never happen, so panic.
  */
-
-ASENTRY_NP(exception_exit)
-	UNWINDSVCFRAME
-	DO_AST
-	PULLFRAMEFROMSVCANDEXIT
-END(exception_exit)
+ASENTRY_NP(reset_entry)
+	mov	r1, lr
+	adr	r0, Lreset_panicmsg
+	b	_C_LABEL(panic)
+	/* NOTREACHED */
+Lreset_panicmsg:
+	.asciz	"Reset vector called, LR = 0x%08x"
+	.balign	4
+END(reset_entry)
 
 /*
- * undefined_entry:
- *
- *	Handler for the Undefined Instruction exception.
- *
- *	We indirect the undefined vector via the handler address
- *	in the data area.  Entry to the undefined handler must
- *	look like direct entry from the vector.
+ * page0 and page0_data -- An image of the ARM vectors which is copied to
+ * the ARM vectors page (high or low) as part of CPU initialization.  The
+ * code that does the copy assumes that page0_data holds one 32-bit word
+ * of data for each of the predefined ARM vectors.  It also assumes that
+ * page0_data follows the vectors in page0, but other stuff can appear 
+ * between the two.  We currently leave room between the two for some fiq 
+ * handler code to be copied in.
  */
-ASENTRY_NP(undefined_entry)
+	.global	_C_LABEL(page0), _C_LABEL(page0_data)
 
-        sub     lr, lr, #0x00000004     /* Adjust the lr */
-	PUSHFRAMEINSVC			/* Push trap frame and switch */
-					/* to SVC32 mode */
-	ldr	r1, Lundefined_handler_address
-	adr	lr, exception_exit
-	mov	r0, sp			/* pass the stack pointer as r0 */
-	ldr	pc, [r1]
-END(undefined_entry)
+_C_LABEL(page0):
+	ldr	pc, .Lreset_entry
+	ldr	pc, .Lundefined_entry
+	ldr	pc, .Lswi_entry
+	ldr	pc, .Lprefetch_abort_entry
+	ldr	pc, .Ldata_abort_entry
+	ldr	pc, .Laddr_exception_entry
+	ldr	pc, .Lirq_entry
+.fiqv:	ldr	pc, .Lfiq_entry
+	.space 256	/* room for some fiq handler code */
+
+_C_LABEL(page0_data):
+.Lreset_entry:		.word	reset_entry
+.Lundefined_entry:	.word	undefined_entry
+.Lswi_entry:		.word	swi_entry
+.Lprefetch_abort_entry:	.word	prefetch_abort_entry
+.Ldata_abort_entry:	.word	data_abort_entry
+.Laddr_exception_entry:	.word	addr_exception_entry
+.Lirq_entry:		.word	irq_entry
+.Lfiq_entry:		.word	fiq_entry
 
-ASENTRY_NP(undefinedinstruction_bounce)
-	b	undefinedinstruction
-END(undefinedinstruction_bounce)
+/*
+ * These items are used by the code in fiq.c to install what it calls the
+ * "null" handler.  It's actually our default vector entry that just jumps
+ * to the default handler which just disables FIQs and returns.
+ */
+	.global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size)
 
-Lundefined_handler_address:
-	.word	_C_LABEL(undefined_handler_address)
+_C_LABEL(fiq_nullhandler_code):
+	.word	.fiqv
+_C_LABEL(fiq_nullhandler_size):
+	.word	4
 
-	.data
-	.global	_C_LABEL(undefined_handler_address)
-_C_LABEL(undefined_handler_address):
-	.word	undefinedinstruction_bounce
 
diff --git a/sys/arm/arm/fiq.c b/sys/arm/arm/fiq.c
index f990812..d9dbb5e 100644
--- a/sys/arm/arm/fiq.c
+++ b/sys/arm/arm/fiq.c
@@ -51,8 +51,8 @@ __FBSDID("$FreeBSD$");
 TAILQ_HEAD(, fiqhandler) fiqhandler_stack =
     TAILQ_HEAD_INITIALIZER(fiqhandler_stack);
 
-extern char fiqvector[];
-extern char fiq_nullhandler[], fiq_nullhandler_end[];
+extern char *fiq_nullhandler_code;
+extern uint32_t fiq_nullhandler_size;
 
 #define	IRQ_BIT		I32_bit
 #define	FIQ_BIT		F32_bit
@@ -61,6 +61,9 @@ extern char fiq_nullhandler[], fiq_nullhandler_end[];
  * fiq_installhandler:
  *
  *	Actually install the FIQ handler down at the FIQ vector.
+ *	
+ *	The FIQ vector is fixed by the hardware definition as the
+ *	seventh 32-bit word in the vector page.
  *
  *	Note: If the FIQ is invoked via an extra layer of
  *	indirection, the actual FIQ code store lives in the
@@ -70,11 +73,13 @@ extern char fiq_nullhandler[], fiq_nullhandler_end[];
 static void
 fiq_installhandler(void *func, size_t size)
 {
+	const uint32_t fiqvector = 7 * sizeof(uint32_t);
+
 #if !defined(__ARM_FIQ_INDIRECT)
 	vector_page_setprot(VM_PROT_READ|VM_PROT_WRITE);
 #endif
 
-	memcpy(vector_page + fiqvector, func, size);
+	memcpy((void *)(vector_page + fiqvector), func, size);
 
 #if !defined(__ARM_FIQ_INDIRECT)
 	vector_page_setprot(VM_PROT_READ);
@@ -159,8 +164,7 @@ fiq_release(struct fiqhandler *fh)
 
 	if (TAILQ_FIRST(&fiqhandler_stack) == NULL) {
 		/* Copy the NULL handler back down into the vector. */
-		fiq_installhandler(fiq_nullhandler,
-		    (size_t)(fiq_nullhandler_end - fiq_nullhandler));
+		fiq_installhandler(fiq_nullhandler_code, fiq_nullhandler_size);
 
 		/* Make sure FIQs are disabled when we return. */
 		oldirqstate |= FIQ_BIT;
diff --git a/sys/arm/arm/fiq_subr.S b/sys/arm/arm/fiq_subr.S
index a9df9bf..acb3768 100644
--- a/sys/arm/arm/fiq_subr.S
+++ b/sys/arm/arm/fiq_subr.S
@@ -91,13 +91,3 @@ ENTRY(fiq_setregs)
 	RET
 END(fiq_setregs)
 
-/*
- * fiq_nullhandler:
- *
- *	Null handler copied down to the FIQ vector when the last
- *	FIQ handler is removed.
- */
-	.global	_C_LABEL(fiq_nullhandler), _C_LABEL(fiq_nullhandler_end)
-_C_LABEL(fiq_nullhandler):
-	subs	pc, lr, #4
-_C_LABEL(fiq_nullhandler_end):
diff --git a/sys/arm/arm/fusu.S b/sys/arm/arm/fusu.S
index 60b3727..316962d 100644
--- a/sys/arm/arm/fusu.S
+++ b/sys/arm/arm/fusu.S
@@ -34,7 +34,6 @@
  */
 
 #include <machine/asm.h>
-#include <machine/asmacros.h>
 #include <machine/armreg.h>
 #include "assym.s"
 __FBSDID("$FreeBSD$");
diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c
index f7ecff9..9a0c46f 100644
--- a/sys/arm/arm/identcpu.c
+++ b/sys/arm/arm/identcpu.c
@@ -69,36 +69,6 @@ static const char * const generic_steppings[16] = {
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 
-static const char * const sa110_steppings[16] = {
-	"rev 0",	"step J",	"step K",	"step S",
-	"step T",	"rev 5",	"rev 6",	"rev 7",
-	"rev 8",	"rev 9",	"rev 10",	"rev 11",
-	"rev 12",	"rev 13",	"rev 14",	"rev 15",
-};
-
-static const char * const sa1100_steppings[16] = {
-	"rev 0",	"step B",	"step C",	"rev 3",
-	"rev 4",	"rev 5",	"rev 6",	"rev 7",
-	"step D",	"step E",	"rev 10"	"step G",
-	"rev 12",	"rev 13",	"rev 14",	"rev 15",
-};
-
-static const char * const sa1110_steppings[16] = {
-	"step A-0",	"rev 1",	"rev 2",	"rev 3",
-	"step B-0",	"step B-1",	"step B-2",	"step B-3",
-	"step B-4",	"step B-5",	"rev 10",	"rev 11",
-	"rev 12",	"rev 13",	"rev 14",	"rev 15",
-};
-
-static const char * const ixp12x0_steppings[16] = {
-	"(IXP1200 step A)",		"(IXP1200 step B)",
-	"rev 2",			"(IXP1200 step C)",
-	"(IXP1200 step D)",		"(IXP1240/1250 step A)",
-	"(IXP1240 step B)",		"(IXP1250 step B)",
-	"rev 8",	"rev 9",	"rev 10",	"rev 11",
-	"rev 12",	"rev 13",	"rev 14",	"rev 15",
-};
-
 static const char * const xscale_steppings[16] = {
 	"step A-0",	"step A-1",	"step B-0",	"step C-0",
 	"step D-0",	"rev 5",	"rev 6",	"rev 7",
@@ -168,43 +138,6 @@ struct cpuidtab {
 };
 
 const struct cpuidtab cpuids[] = {
-	{ CPU_ID_ARM2,		CPU_CLASS_ARM2,		"ARM2",
-	  generic_steppings },
-	{ CPU_ID_ARM250,	CPU_CLASS_ARM2AS,	"ARM250",
-	  generic_steppings },
-
-	{ CPU_ID_ARM3,		CPU_CLASS_ARM3,		"ARM3",
-	  generic_steppings },
-
-	{ CPU_ID_ARM600,	CPU_CLASS_ARM6,		"ARM600",
-	  generic_steppings },
-	{ CPU_ID_ARM610,	CPU_CLASS_ARM6,		"ARM610",
-	  generic_steppings },
-	{ CPU_ID_ARM620,	CPU_CLASS_ARM6,		"ARM620",
-	  generic_steppings },
-
-	{ CPU_ID_ARM700,	CPU_CLASS_ARM7,		"ARM700",
-	  generic_steppings },
-	{ CPU_ID_ARM710,	CPU_CLASS_ARM7,		"ARM710",
-	  generic_steppings },
-	{ CPU_ID_ARM7500,	CPU_CLASS_ARM7,		"ARM7500",
-	  generic_steppings },
-	{ CPU_ID_ARM710A,	CPU_CLASS_ARM7,		"ARM710a",
-	  generic_steppings },
-	{ CPU_ID_ARM7500FE,	CPU_CLASS_ARM7,		"ARM7500FE",
-	  generic_steppings },
-	{ CPU_ID_ARM710T,	CPU_CLASS_ARM7TDMI,	"ARM710T",
-	  generic_steppings },
-	{ CPU_ID_ARM720T,	CPU_CLASS_ARM7TDMI,	"ARM720T",
-	  generic_steppings },
-	{ CPU_ID_ARM740T8K,	CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)",
-	  generic_steppings },
-	{ CPU_ID_ARM740T4K,	CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)",
-	  generic_steppings },
-
-	{ CPU_ID_ARM810,	CPU_CLASS_ARM8,		"ARM810",
-	  generic_steppings },
-
 	{ CPU_ID_ARM920T,	CPU_CLASS_ARM9TDMI,	"ARM920T",
 	  generic_steppings },
 	{ CPU_ID_ARM920T_ALT,	CPU_CLASS_ARM9TDMI,	"ARM920T",
@@ -255,16 +188,6 @@ const struct cpuidtab cpuids[] = {
 	{ CPU_ID_KRAIT,		CPU_CLASS_KRAIT,	"Krait",
 	  generic_steppings },
 
-	{ CPU_ID_SA110,		CPU_CLASS_SA1,		"SA-110",
-	  sa110_steppings },
-	{ CPU_ID_SA1100,	CPU_CLASS_SA1,		"SA-1100",
-	  sa1100_steppings },
-	{ CPU_ID_SA1110,	CPU_CLASS_SA1,		"SA-1110",
-	  sa1110_steppings },
-
-	{ CPU_ID_IXP1200,	CPU_CLASS_SA1,		"IXP1200",
-	  ixp12x0_steppings },
-
 	{ CPU_ID_80200,		CPU_CLASS_XSCALE,	"i80200",
 	  xscale_steppings },
 
@@ -340,13 +263,6 @@ struct cpu_classtab {
 
 const struct cpu_classtab cpu_classes[] = {
 	{ "unknown",	NULL },			/* CPU_CLASS_NONE */
-	{ "ARM2",	"CPU_ARM2" },		/* CPU_CLASS_ARM2 */
-	{ "ARM2as",	"CPU_ARM250" },		/* CPU_CLASS_ARM2AS */
-	{ "ARM3",	"CPU_ARM3" },		/* CPU_CLASS_ARM3 */
-	{ "ARM6",	"CPU_ARM6" },		/* CPU_CLASS_ARM6 */
-	{ "ARM7",	"CPU_ARM7" },		/* CPU_CLASS_ARM7 */
-	{ "ARM7TDMI",	"CPU_ARM7TDMI" },	/* CPU_CLASS_ARM7TDMI */
-	{ "ARM8",	"CPU_ARM8" },		/* CPU_CLASS_ARM8 */
 	{ "ARM9TDMI",	"CPU_ARM9TDMI" },	/* CPU_CLASS_ARM9TDMI */
 	{ "ARM9E-S",	"CPU_ARM9E" },		/* CPU_CLASS_ARM9ES */
 	{ "ARM9EJ-S",	"CPU_ARM9E" },		/* CPU_CLASS_ARM9EJS */
@@ -354,7 +270,6 @@ const struct cpu_classtab cpu_classes[] = {
 	{ "ARM10EJ",	"CPU_ARM10" },		/* CPU_CLASS_ARM10EJ */
 	{ "Cortex-A",	"CPU_CORTEXA" },	/* CPU_CLASS_CORTEXA */
 	{ "Krait",	"CPU_KRAIT" },		/* CPU_CLASS_KRAIT */
-	{ "SA-1",	"CPU_SA110" },		/* CPU_CLASS_SA1 */
 	{ "XScale",	"CPU_XSCALE_..." },	/* CPU_CLASS_XSCALE */
 	{ "ARM11J",	"CPU_ARM11" },		/* CPU_CLASS_ARM11J */
 	{ "Marvell",	"CPU_MARVELL" },	/* CPU_CLASS_MARVELL */
@@ -493,18 +408,11 @@ identify_arm_cpu(void)
 			printf(" Little-endian");
 
 		switch (cpu_class) {
-		case CPU_CLASS_ARM6:
-		case CPU_CLASS_ARM7:
-		case CPU_CLASS_ARM7TDMI:
-		case CPU_CLASS_ARM8:
-			print_enadis(ctrl & CPU_CONTROL_IDC_ENABLE, "IDC");
-			break;
 		case CPU_CLASS_ARM9TDMI:
 		case CPU_CLASS_ARM9ES:
 		case CPU_CLASS_ARM9EJS:
 		case CPU_CLASS_ARM10E:
 		case CPU_CLASS_ARM10EJ:
-		case CPU_CLASS_SA1:
 		case CPU_CLASS_XSCALE:
 		case CPU_CLASS_ARM11J:
 		case CPU_CLASS_MARVELL:
diff --git a/sys/arm/arm/intr.c b/sys/arm/arm/intr.c
index 9c3365d..ac93cbd 100644
--- a/sys/arm/arm/intr.c
+++ b/sys/arm/arm/intr.c
@@ -56,12 +56,18 @@ typedef void (*mask_fn)(void *);
 
 static struct intr_event *intr_events[NIRQ];
 
-void	arm_handler_execute(struct trapframe *, int);
+void	arm_irq_handler(struct trapframe *);
 
 void (*arm_post_filter)(void *) = NULL;
 int (*arm_config_irq)(int irq, enum intr_trigger trig,
     enum intr_polarity pol) = NULL;
 
+/* Data for statistics reporting. */
+u_long intrcnt[NIRQ];
+char intrnames[NIRQ * INTRNAME_LEN];
+size_t sintrcnt = sizeof(intrcnt);
+size_t sintrnames = sizeof(intrnames);
+
 /*
  * Pre-format intrnames into an array of fixed-size strings containing spaces.
  * This allows us to avoid the need for an intermediate table of indices into
@@ -127,7 +133,7 @@ dosoftints(void)
 }
 
 void
-arm_handler_execute(struct trapframe *frame, int irqnb)
+arm_irq_handler(struct trapframe *frame)
 {
 	struct intr_event *event;
 	int i;
diff --git a/sys/arm/arm/irq_dispatch.S b/sys/arm/arm/irq_dispatch.S
deleted file mode 100644
index 258782f..0000000
--- a/sys/arm/arm/irq_dispatch.S
+++ /dev/null
@@ -1,120 +0,0 @@
-/*	$NetBSD: irq_dispatch.S,v 1.5 2003/10/30 08:57:24 scw Exp $	*/
-
-/*-
- * Copyright (c) 2002 Fujitsu Component Limited
- * Copyright (c) 2002 Genetec Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of The Fujitsu Component Limited nor the name of
- *    Genetec corporation may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
- * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
- * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- */
-
-/*-
- * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "assym.s"
-#include <machine/asm.h>
-#include <machine/asmacros.h>
-#include <machine/armreg.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * irq_entry:
- *	Main entry point for the IRQ vector.  This is a generic version
- *	which can be used by different platforms.
- */
-	.text
-	.align	0
-
-.Lcurrent_intr_depth:
-	.word	_C_LABEL(current_intr_depth)
-AST_LOCALS
-
-ASENTRY_NP(irq_entry)
-	sub	lr, lr, #0x00000004	/* Adjust the lr */
-	PUSHFRAMEINSVC			/* Push an interrupt frame */
-	UNWINDSVCFRAME
-	mov	r0, sp			/* arg for dispatcher */
-
-	mov	r1, #0
-	bl	_C_LABEL(arm_handler_execute)
-
-	DO_AST
-	PULLFRAMEFROMSVCANDEXIT
-	movs	pc, lr			/* Exit */
-END(irq_entry)
-
-	.data
-	.align	0
-
-	.global _C_LABEL(intrnames), _C_LABEL(sintrnames)
-	.global _C_LABEL(intrcnt), _C_LABEL(sintrcnt)
-_C_LABEL(intrnames):
-	.space NIRQ * (MAXCOMLEN + 1)
-_C_LABEL(intrcnt):
-	.space NIRQ * 4
-_C_LABEL(sintrnames):
-	.int NIRQ * (MAXCOMLEN + 1)
-_C_LABEL(sintrcnt):
-	.int NIRQ * 4
-
-	.global _C_LABEL(current_intr_depth)
-_C_LABEL(current_intr_depth):
-	.word	0
-
diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c
index 9fb2ffc..b9e46b8 100644
--- a/sys/arm/arm/machdep.c
+++ b/sys/arm/arm/machdep.c
@@ -143,10 +143,6 @@ extern vm_offset_t ksym_start, ksym_end;
 
 static struct pv_addr kernel_pt_table[KERNEL_PT_MAX];
 
-extern u_int data_abort_handler_address;
-extern u_int prefetch_abort_handler_address;
-extern u_int undefined_handler_address;
-
 vm_paddr_t pmap_pa;
 
 struct pv_addr systempage;
@@ -1279,10 +1275,6 @@ initarm(struct arm_boot_params *abp)
 	 */
 	cpu_idcache_wbinv_all();
 
-	/* Set stack for exception handlers */
-	data_abort_handler_address = (u_int)data_abort_handler;
-	prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
-	undefined_handler_address = (u_int)undefinedinstruction_bounce;
 	undefined_init();
 
 	init_proc0(kernelstack.pv_va);
diff --git a/sys/arm/arm/pmap.c b/sys/arm/arm/pmap.c
index 9bd53fa..d19306d 100644
--- a/sys/arm/arm/pmap.c
+++ b/sys/arm/arm/pmap.c
@@ -458,7 +458,7 @@ kernel_pt_lookup(vm_paddr_t pa)
 	return (0);
 }
 
-#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
+#if ARM_MMU_GENERIC != 0
 void
 pmap_pte_init_generic(void)
 {
@@ -500,23 +500,6 @@ pmap_pte_init_generic(void)
 	pmap_zero_page_func = pmap_zero_page_generic;
 }
 
-#if defined(CPU_ARM8)
-void
-pmap_pte_init_arm8(void)
-{
-
-	/*
-	 * ARM8 is compatible with generic, but we need to use
-	 * the page tables uncached.
-	 */
-	pmap_pte_init_generic();
-
-	pte_l1_s_cache_mode_pt = 0;
-	pte_l2_l_cache_mode_pt = 0;
-	pte_l2_s_cache_mode_pt = 0;
-}
-#endif /* CPU_ARM8 */
-
 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
 void
 pmap_pte_init_arm9(void)
@@ -537,7 +520,7 @@ pmap_pte_init_arm9(void)
 	pte_l2_s_cache_mode_pt = L2_C;
 }
 #endif /* CPU_ARM9 */
-#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
+#endif /* ARM_MMU_GENERIC != 0 */
 
 #if defined(CPU_ARM10)
 void
@@ -561,27 +544,6 @@ pmap_pte_init_arm10(void)
 }
 #endif /* CPU_ARM10 */
 
-#if  ARM_MMU_SA1 == 1
-void
-pmap_pte_init_sa1(void)
-{
-
-	/*
-	 * The StrongARM SA-1 cache does not have a write-through
-	 * mode.  So, do the generic initialization, then reset
-	 * the page table cache mode to B=1,C=1, and note that
-	 * the PTEs need to be sync'd.
-	 */
-	pmap_pte_init_generic();
-
-	pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
-	pte_l2_l_cache_mode_pt = L2_B|L2_C;
-	pte_l2_s_cache_mode_pt = L2_B|L2_C;
-
-	pmap_needs_pte_sync = 1;
-}
-#endif /* ARM_MMU_SA1 == 1*/
-
 #if ARM_MMU_XSCALE == 1
 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
 static u_int xscale_use_minidata;
@@ -1972,34 +1934,6 @@ pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
 		rv = 1;
 	}
 
-#ifdef CPU_SA110
-	/*
-	 * There are bugs in the rev K SA110.  This is a check for one
-	 * of them.
-	 */
-	if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
-	    curcpu()->ci_arm_cpurev < 3) {
-		/* Always current pmap */
-		if (l2pte_valid(pte)) {
-			extern int kernel_debug;
-			if (kernel_debug & 1) {
-				struct proc *p = curlwp->l_proc;
-				printf("prefetch_abort: page is already "
-				    "mapped - pte=%p *pte=%08x\n", ptep, pte);
-				printf("prefetch_abort: pc=%08lx proc=%p "
-				    "process=%s\n", va, p, p->p_comm);
-				printf("prefetch_abort: far=%08x fs=%x\n",
-				    cpu_faultaddress(), cpu_faultstatus());
-			}
-#ifdef DDB
-			if (kernel_debug & 2)
-				Debugger();
-#endif
-			rv = 1;
-		}
-	}
-#endif /* CPU_SA110 */
-
 #ifdef DEBUG
 	/*
 	 * If 'rv == 0' at this point, it generally indicates that there is a
@@ -3981,7 +3915,7 @@ pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
  * StrongARM accesses to non-cached pages are non-burst making writing
  * _any_ bulk data very slow.
  */
-#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3)
+#if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_CORE3)
 void
 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
 {
@@ -4008,7 +3942,7 @@ pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
 
 	mtx_unlock(&cmtx);
 }
-#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
+#endif /* ARM_MMU_GENERIC != 0 */
 
 #if ARM_MMU_XSCALE == 1
 void
@@ -4224,7 +4158,7 @@ pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
  * hook points. The same comment regarding cachability as in
  * pmap_zero_page also applies here.
  */
-#if  (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3)
+#if ARM_MMU_GENERIC != 0 || defined (CPU_XSCALE_CORE3)
 void
 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
 {
@@ -4289,7 +4223,7 @@ pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
 	cpu_l2cache_inv_range(csrcp + a_offs, cnt);
 	cpu_l2cache_wbinv_range(cdstp + b_offs, cnt);
 }
-#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
+#endif /* ARM_MMU_GENERIC != 0 */
 
 #if ARM_MMU_XSCALE == 1
 void
diff --git a/sys/arm/arm/support.S b/sys/arm/arm/support.S
index b6d2dbb..9019e33 100644
--- a/sys/arm/arm/support.S
+++ b/sys/arm/arm/support.S
@@ -87,7 +87,6 @@
  */
 
 #include <machine/asm.h>
-#include <machine/asmacros.h>
 __FBSDID("$FreeBSD$");
 
 #include "assym.s"
diff --git a/sys/arm/arm/swtch.S b/sys/arm/arm/swtch.S
index d704823..610d575 100644
--- a/sys/arm/arm/swtch.S
+++ b/sys/arm/arm/swtch.S
@@ -486,21 +486,12 @@ ENTRY(savectx)
 END(savectx)
 
 ENTRY(fork_trampoline)
-	STOP_UNWINDING	/* Can't unwind beyond the thread enty point */
-	mov	r1, r5
+	STOP_UNWINDING	/* EABI: Don't unwind beyond the thread enty point. */
+	mov	fp, #0	/* OABI: Stack traceback via fp stops here. */
 	mov	r2, sp
+	mov	r1, r5
 	mov	r0, r4
-	mov	fp, #0
-	bl	_C_LABEL(fork_exit)
-	/* Kill irq"s */
-	mrs	r0, cpsr
-	orr	r0, r0, #(I32_bit|F32_bit)
-	msr	cpsr_c, r0
-	DO_AST
-	PULLFRAME
-
-	movs	pc, lr			/* Exit */
-
-AST_LOCALS
+	ldr	lr, =swi_exit		/* Go finish forking, then return */
+	b	_C_LABEL(fork_exit)	/* to userland via swi_exit code. */
 END(fork_trampoline)
 
diff --git a/sys/arm/arm/trap.c b/sys/arm/arm/trap.c
index 423e3de..eb919eb 100644
--- a/sys/arm/arm/trap.c
+++ b/sys/arm/arm/trap.c
@@ -126,7 +126,6 @@ __FBSDID("$FreeBSD$");
 
 
 void swi_handler(struct trapframe *);
-void undefinedinstruction(struct trapframe *);
 
 #include <machine/disassem.h>
 #include <machine/machdep.h>
@@ -137,11 +136,6 @@ extern char fusubailout[];
 int last_fault_code;	/* For the benefit of pmap_fault_fixup() */
 #endif
 
-#if defined(CPU_ARM7TDMI)
-/* These CPUs may need data/prefetch abort fixups */
-#define	CPU_ABORT_FIXUP_REQUIRED
-#endif
-
 struct ksig {
 	int signb;
 	u_long code;
@@ -201,37 +195,6 @@ call_trapsignal(struct thread *td, int sig, u_long code)
 	trapsignal(td, &ksi);
 }
 
-static __inline int
-data_abort_fixup(struct trapframe *tf, u_int fsr, u_int far, struct thread *td,
-    struct ksig *ksig)
-{
-#ifdef CPU_ABORT_FIXUP_REQUIRED
-	int error;
-
-	/* Call the cpu specific data abort fixup routine */
-	error = cpu_dataabt_fixup(tf);
-	if (__predict_true(error != ABORT_FIXUP_FAILED))
-		return (error);
-
-	/*
-	 * Oops, couldn't fix up the instruction
-	 */
-	printf("data_abort_fixup: fixup for %s mode data abort failed.\n",
-	    TRAP_USERMODE(tf) ? "user" : "kernel");
-	printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
-	    *((u_int *)tf->tf_pc));
-	disassemble(tf->tf_pc);
-
-	/* Die now if this happened in kernel mode */
-	if (!TRAP_USERMODE(tf))
-		dab_fatal(tf, fsr, far, td, NULL, ksig);
-
-	return (error);
-#else
-	return (ABORT_FIXUP_OK);
-#endif /* CPU_ABORT_FIXUP_REQUIRED */
-}
-
 void
 data_abort_handler(struct trapframe *tf)
 {
@@ -341,19 +304,6 @@ data_abort_handler(struct trapframe *tf)
 		dab_fatal(tf, fsr, far, td, &ksig);
 	}
 
-	/* See if the cpu state needs to be fixed up */
-	switch (data_abort_fixup(tf, fsr, far, td, &ksig)) {
-	case ABORT_FIXUP_RETURN:
-		return;
-	case ABORT_FIXUP_FAILED:
-		/* Deliver a SIGILL to the process */
-		ksig.signb = SIGILL;
-		ksig.code = 0;
-		goto do_trapsignal;
-	default:
-		break;
-	}
-
 	va = trunc_page((vm_offset_t)far);
 
 	/*
@@ -562,9 +512,6 @@ dab_align(struct trapframe *tf, u_int fsr, u_int far, struct thread *td,
 
 	/* pcb_onfault *must* be NULL at this point */
 
-	/* See if the cpu state needs to be fixed up */
-	(void) data_abort_fixup(tf, fsr, far, td, ksig);
-
 	/* Deliver a bus error signal to the process */
 	ksig->code = 0;
 	ksig->signb = SIGBUS;
@@ -653,9 +600,6 @@ dab_buserr(struct trapframe *tf, u_int fsr, u_int far, struct thread *td,
 		return (0);
 	}
 
-	/* See if the cpu state needs to be fixed up */
-	(void) data_abort_fixup(tf, fsr, far, td, ksig);
-
 	/*
 	 * At this point, if the fault happened in kernel mode, we're toast
 	 */
@@ -670,37 +614,6 @@ dab_buserr(struct trapframe *tf, u_int fsr, u_int far, struct thread *td,
 	return (1);
 }
 
-static __inline int
-prefetch_abort_fixup(struct trapframe *tf, struct ksig *ksig)
-{
-#ifdef CPU_ABORT_FIXUP_REQUIRED
-	int error;
-
-	/* Call the cpu specific prefetch abort fixup routine */
-	error = cpu_prefetchabt_fixup(tf);
-	if (__predict_true(error != ABORT_FIXUP_FAILED))
-		return (error);
-
-	/*
-	 * Oops, couldn't fix up the instruction
-	 */
-	printf(
-	    "prefetch_abort_fixup: fixup for %s mode prefetch abort failed.\n",
-	    TRAP_USERMODE(tf) ? "user" : "kernel");
-	printf("pc = 0x%08x, opcode 0x%08x, insn = ", tf->tf_pc,
-	    *((u_int *)tf->tf_pc));
-	disassemble(tf->tf_pc);
-
-	/* Die now if this happened in kernel mode */
-	if (!TRAP_USERMODE(tf))
-		dab_fatal(tf, 0, tf->tf_pc, NULL, ksig);
-
-	return (error);
-#else
-	return (ABORT_FIXUP_OK);
-#endif /* CPU_ABORT_FIXUP_REQUIRED */
-}
-
 /*
  * void prefetch_abort_handler(struct trapframe *tf)
  *
@@ -749,20 +662,6 @@ prefetch_abort_handler(struct trapframe *tf)
 			enable_interrupts(F32_bit);
 	}
 
-	/* See if the cpu state needs to be fixed up */
-	switch (prefetch_abort_fixup(tf, &ksig)) {
-	case ABORT_FIXUP_RETURN:
-		return;
-	case ABORT_FIXUP_FAILED:
-		/* Deliver a SIGILL to the process */
-		ksig.signb = SIGILL;
-		ksig.code = 0;
-		td->td_frame = tf;
-		goto do_trapsignal;
-	default:
-		break;
-	}
-
 	/* Prefetch aborts cannot happen in kernel mode */
 	if (__predict_false(!TRAP_USERMODE(tf)))
 		dab_fatal(tf, 0, tf->tf_pc, NULL, &ksig);
diff --git a/sys/arm/arm/vectors.S b/sys/arm/arm/vectors.S
deleted file mode 100644
index 95ee5d1..0000000
--- a/sys/arm/arm/vectors.S
+++ /dev/null
@@ -1,104 +0,0 @@
-/*	$NetBSD: vectors.S,v 1.4 2002/08/17 16:36:32 thorpej Exp $	*/
-
-/*-
- * Copyright (C) 1994-1997 Mark Brinicombe
- * Copyright (C) 1994 Brini
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Brini.
- * 4. The name of Brini may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <machine/asm.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * These are the exception vectors copied down to page 0.
- *
- * Note that FIQs are special; rather than using a level of
- * indirection, we actually copy the FIQ code down into the
- * vector page.
- */
-
-	.text
-	.align	0
-	.global	_C_LABEL(page0), _C_LABEL(page0_data), _C_LABEL(page0_end)
-	.global _C_LABEL(fiqvector)
-
-_C_LABEL(page0):
-	ldr	pc, .Lreset_target
-	ldr	pc, .Lundefined_target
-	ldr	pc, .Lswi_target
-	ldr	pc, .Lprefetch_abort_target
-	ldr	pc, .Ldata_abort_target
-	ldr	pc, .Laddress_exception_target
-	ldr	pc, .Lirq_target
-#ifdef __ARM_FIQ_INDIRECT
-	ldr	pc, .Lfiq_target
-#else
-.Lfiqvector:
-	.set	_C_LABEL(fiqvector), . - _C_LABEL(page0)
-	subs	pc, lr, #4
-	.org	.Lfiqvector + 0x100
-#endif
-
-_C_LABEL(page0_data):
-.Lreset_target:
-	.word	reset_entry
-
-.Lundefined_target:
-	.word	undefined_entry
-
-.Lswi_target:
-	.word	swi_entry
-
-.Lprefetch_abort_target:
-	.word	prefetch_abort_entry
-
-.Ldata_abort_target:
-	.word	data_abort_entry
-
-.Laddress_exception_target:
-	.word	address_exception_entry
-
-.Lirq_target:
-	.word	irq_entry
-
-#ifdef __ARM_FIQ_INDIRECT
-.Lfiq_target:
-	.word	_C_LABEL(fiqvector)
-#else
-	.word	0	/* pad it out */
-#endif
-_C_LABEL(page0_end):
-
-#ifdef __ARM_FIQ_INDIRECT
-	.data
-	.align	0
-_C_LABEL(fiqvector):
-	subs	pc, lr, #4
-	.org	_C_LABEL(fiqvector) + 0x100
-#endif