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authorian <ian@FreeBSD.org>2014-05-14 17:40:18 +0000
committerian <ian@FreeBSD.org>2014-05-14 17:40:18 +0000
commit3c9602820517b21689d8a6153fd6f7ea38c7a749 (patch)
tree5a1c9e79488178b15f78d541f8a651be6ee21573 /sys/arm/arm/swtch.S
parent4ee6f0bd3bade07595ecc84f07aa45d765a3eae1 (diff)
downloadFreeBSD-src-3c9602820517b21689d8a6153fd6f7ea38c7a749.zip
FreeBSD-src-3c9602820517b21689d8a6153fd6f7ea38c7a749.tar.gz
MFC r258359, r258742, r258845, r259936, r259640
Apply access flags for managed and unmanaged pages properly on ARMv6/v7 Set the PGA_WRITEABLE flag when the protections indicate write access, not just when the current access is a write. Enable missing Access Flag for secondary cores on ARMv6/v7 Add identification and necessary type checks for Krait CPU cores.
Diffstat (limited to 'sys/arm/arm/swtch.S')
-rw-r--r--sys/arm/arm/swtch.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/arm/arm/swtch.S b/sys/arm/arm/swtch.S
index 95a37cf..bff20fb 100644
--- a/sys/arm/arm/swtch.S
+++ b/sys/arm/arm/swtch.S
@@ -131,7 +131,7 @@ ENTRY(cpu_throw)
/* Switch to lwp0 context */
ldr r9, .Lcpufuncs
-#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
+#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT)
mov lr, pc
ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
#endif
@@ -361,7 +361,7 @@ ENTRY(cpu_switch)
cmpeq r0, r5 /* Same DACR? */
beq .Lcs_context_switched /* yes! */
-#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
+#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT)
/*
* Definately need to flush the cache.
*/
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