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| author | ian <ian@FreeBSD.org> | 2015-02-12 03:50:33 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2015-02-12 03:50:33 +0000 |
| commit | dff1ee7f45c73c94ead5792fd2f879e70e6232c8 (patch) | |
| tree | 7c6cdeb383764776a348de294da4e685c265f42c /sys/arm/arm/exception.S | |
| parent | 0a5ffc45680c62f19448a2d2f49d063715444a28 (diff) | |
| download | FreeBSD-src-dff1ee7f45c73c94ead5792fd2f879e70e6232c8.zip FreeBSD-src-dff1ee7f45c73c94ead5792fd2f879e70e6232c8.tar.gz | |
MFC r271394, r271398:
Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE
from asm.h as they were already defined in armreg.h.
Unify interrupts bit definition and usage. While here remove PSR_C_bit.
Diffstat (limited to 'sys/arm/arm/exception.S')
| -rw-r--r-- | sys/arm/arm/exception.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sys/arm/arm/exception.S b/sys/arm/arm/exception.S index 7f79654..5cef965 100644 --- a/sys/arm/arm/exception.S +++ b/sys/arm/arm/exception.S @@ -244,12 +244,12 @@ __FBSDID("$FreeBSD$"); #define DO_AST \ ldr r0, [sp] /* Get the SPSR from stack */ ;\ mrs r4, cpsr /* save CPSR */ ;\ - orr r1, r4, #(I32_bit|F32_bit) ;\ + orr r1, r4, #(PSR_I|PSR_F) ;\ msr cpsr_c, r1 /* Disable interrupts */ ;\ and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ teq r0, #(PSR_USR32_MODE) ;\ bne 2f /* Nope, get out now */ ;\ - bic r4, r4, #(I32_bit|F32_bit) ;\ + bic r4, r4, #(PSR_I|PSR_F) ;\ 1: GET_CURTHREAD_PTR(r5) ;\ ldr r1, [r5, #(TD_FLAGS)] ;\ and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED) ;\ @@ -258,7 +258,7 @@ __FBSDID("$FreeBSD$"); msr cpsr_c, r4 /* Restore interrupts */ ;\ mov r0, sp ;\ bl _C_LABEL(ast) /* ast(frame) */ ;\ - orr r0, r4, #(I32_bit|F32_bit) ;\ + orr r0, r4, #(PSR_I|PSR_F) ;\ msr cpsr_c, r0 ;\ b 1b ;\ 2: @@ -382,7 +382,7 @@ END(irq_entry) */ ASENTRY_NP(fiq_entry) mrs r8, cpsr /* FIQ handling isn't supported, */ - bic r8, #(F32_bit) /* just disable FIQ and return. */ + bic r8, #(PSR_F) /* just disable FIQ and return. */ msr cpsr_c, r8 /* The r8 we trash here is the */ subs pc, lr, #4 /* banked FIQ-mode r8. */ END(fiq_entry) |
