Add simple clock driver and ehci glue code for a10

Update dts and kernel config

Approved by: gonzo@

4 files changed, 566 insertions, 0 deletions

diff --git a/sys/arm/allwinner/a10_clk.c b/sys/arm/allwinner/a10_clk.c
new file mode 100644
index 0000000..2d7699e
--- /dev/null
+++ b/sys/arm/allwinner/a10_clk.c
@@ -0,0 +1,171 @@
+/*-
+ * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@gmail.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Simple clock driver for Allwinner A10 */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+#include <sys/watchdog.h>
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/frame.h>
+#include <machine/intr.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+
+#include "a10_clk.h"
+
+struct a10_ccm_softc {
+	struct resource		*res;
+	bus_space_tag_t		bst;
+	bus_space_handle_t	bsh;
+};
+
+static struct a10_ccm_softc *a10_ccm_sc = NULL;
+
+#define ccm_read_4(reg)			\
+	bus_space_read_4(a10_ccm_sc->bst, a10_ccm_sc->bsh, reg)
+#define ccm_write_4(reg, val)		\
+	bus_space_write_4(a10_ccm_sc->bst, a10_ccm_sc->bsh, reg, val)
+
+static int
+a10_ccm_probe(device_t dev)
+{
+	if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) {
+		device_set_desc(dev, "Allwinner Clock Control Module");
+		return(BUS_PROBE_DEFAULT);
+	}
+
+	return (ENXIO);
+}
+
+static int
+a10_ccm_attach(device_t dev)
+{
+	struct a10_ccm_softc *sc = device_get_softc(dev);
+	int rid = 0;
+
+	if (a10_ccm_sc)
+		return (ENXIO);
+
+	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (!sc->res) {
+		device_printf(dev, "could not allocate resource\n");
+		return (ENXIO);
+	}
+
+	sc->bst = rman_get_bustag(sc->res);
+	sc->bsh = rman_get_bushandle(sc->res);
+
+	a10_ccm_sc = sc;
+
+	return (0);
+}
+
+static device_method_t a10_ccm_methods[] = {
+	DEVMETHOD(device_probe,		a10_ccm_probe),
+	DEVMETHOD(device_attach,	a10_ccm_attach),
+	{ 0, 0 }
+};
+
+static driver_t a10_ccm_driver = {
+	"a10_ccm",
+	a10_ccm_methods,
+	sizeof(struct a10_ccm_softc),
+};
+
+static devclass_t a10_ccm_devclass;
+
+DRIVER_MODULE(a10_ccm, simplebus, a10_ccm_driver, a10_ccm_devclass, 0, 0);
+
+int
+a10_clk_usb_activate(void)
+{
+	struct a10_ccm_softc *sc = a10_ccm_sc;
+	uint32_t reg_value = 0;
+
+	if (sc == NULL)
+		return ENXIO;
+
+	/* Gating AHB clock for USB */
+	reg_value = ccm_read_4(CCM_AHB_GATING0);
+	reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */
+	reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */
+	ccm_write_4(CCM_AHB_GATING0, reg_value);
+
+	/* Enable clock for USB */
+	reg_value = ccm_read_4(CCM_USB_CLK);
+	reg_value |= CCM_USB_PHY; /* USBPHY */
+	reg_value |= CCM_USB0_RESET; /* disable reset for USB0 */
+	reg_value |= CCM_USB1_RESET; /* disable reset for USB1 */
+	reg_value |= CCM_USB2_RESET; /* disable reset for USB2 */
+	ccm_write_4(CCM_USB_CLK, reg_value);
+
+	return (0);
+}
+
+int
+a10_clk_usb_deactivate(void)
+{
+	struct a10_ccm_softc *sc = a10_ccm_sc;
+	uint32_t reg_value = 0;
+
+	if (sc == NULL)
+		return ENXIO;
+
+	/* Disable clock for USB */
+	reg_value = ccm_read_4(CCM_USB_CLK);
+	reg_value &= ~CCM_USB_PHY; /* USBPHY */
+	reg_value &= ~CCM_USB0_RESET; /* reset for USB0 */
+	reg_value &= ~CCM_USB1_RESET; /* reset for USB1 */
+	reg_value &= ~CCM_USB2_RESET; /* reset for USB2 */
+	ccm_write_4(CCM_USB_CLK, reg_value);
+
+	/* Disable gating AHB clock for USB */
+	reg_value = ccm_read_4(CCM_AHB_GATING0);
+	reg_value &= ~CCM_AHB_GATING_USB0; /* disable AHB clock gate usb0 */
+	reg_value &= ~CCM_AHB_GATING_EHCI1; /* disable AHB clock gate ehci1 */
+	ccm_write_4(CCM_AHB_GATING0, reg_value);
+
+	return (0);
+}
+
diff --git a/sys/arm/allwinner/a10_clk.h b/sys/arm/allwinner/a10_clk.h
new file mode 100644
index 0000000..7316a22
--- /dev/null
+++ b/sys/arm/allwinner/a10_clk.h
@@ -0,0 +1,114 @@
+/*-
+ * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@gmail.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _A10_CLK_H_
+#define _A10_CLK_H_
+
+#define CCMU_BASE		0xe1c20000
+
+#define CCM_PLL1_CFG		0x0000
+#define CCM_PLL1_TUN		0x0004
+#define CCM_PLL2_CFG		0x0008
+#define CCM_PLL2_TUN		0x000c
+#define CCM_PLL3_CFG		0x0010
+#define CCM_PLL3_TUN		0x0014
+#define CCM_PLL4_CFG		0x0018
+#define CCM_PLL4_TUN		0x001c
+#define CCM_PLL5_CFG		0x0020
+#define CCM_PLL5_TUN		0x0024
+#define CCM_PLL6_CFG		0x0028
+#define CCM_PLL6_TUN		0x002c
+#define CCM_PLL7_CFG		0x0030
+#define CCM_PLL7_TUN		0x0034
+#define CCM_PLL1_TUN2		0x0038
+#define CCM_PLL5_TUN2		0x003c
+#define CCM_PLL_LOCK_DBG	0x004c
+#define CCM_OSC24M_CFG		0x0050
+#define CCM_CPU_AHB_APB0_CFG	0x0054
+#define CCM_APB1_CLK_DIV	0x0058
+#define CCM_AXI_GATING		0x005c
+#define CCM_AHB_GATING0		0x0060
+#define CCM_AHB_GATING1		0x0064
+#define CCM_APB0_GATING		0x0068
+#define CCM_APB1_GATING		0x006c
+#define CCM_NAND_SCLK_CFG	0x0080
+#define CCM_MS_SCLK_CFG		0x0084
+#define CCM_MMC0_SCLK_CFG	0x0088
+#define CCM_MMC1_SCLK_CFG	0x008c
+#define CCM_MMC2_SCLK_CFG	0x0090
+#define CCM_MMC3_SCLK_CFG	0x0094
+#define CCM_TS_CLK		0x0098
+#define CCM_SS_CLK		0x009c
+#define CCM_SPI0_CLK		0x00a0
+#define CCM_SPI1_CLK		0x00a4
+#define CCM_SPI2_CLK		0x00a8
+#define CCM_PATA_CLK		0x00ac
+#define CCM_IR0_CLK		0x00b0
+#define CCM_IR1_CLK		0x00b4
+#define CCM_IIS_CLK		0x00b8
+#define CCM_AC97_CLK		0x00bc
+#define CCM_SPDIF_CLK		0x00c0
+#define CCM_KEYPAD_CLK		0x00c4
+#define CCM_SATA_CLK		0x00c8
+#define CCM_USB_CLK		0x00cc
+#define CCM_GPS_CLK		0x00d0
+#define CCM_SPI3_CLK		0x00d4
+#define CCM_DRAM_CLK		0x0100
+#define CCM_BE0_SCLK		0x0104
+#define CCM_BE1_SCLK		0x0108
+#define CCM_FE0_CLK		0x010c
+#define CCM_FE1_CLK		0x0110
+#define CCM_MP_CLK		0x0114
+#define CCM_LCD0_CH0_CLK	0x0118
+#define CCM_LCD1_CH0_CLK	0x011c
+#define CCM_CSI_ISP_CLK		0x0120
+#define CCM_TVD_CLK		0x0128
+#define CCM_LCD0_CH1_CLK	0x012c
+#define CCM_LCD1_CH1_CLK	0x0130
+#define CCM_CS0_CLK		0x0134
+#define CCM_CS1_CLK		0x0138
+#define CCM_VE_CLK		0x013c
+#define CCM_AUDIO_CODEC_CLK	0x0140
+#define CCM_AVS_CLK		0x0144
+#define CCM_ACE_CLK		0x0148
+#define CCM_LVDS_CLK		0x014c
+#define CCM_HDMI_CLK		0x0150
+#define CCM_MALI400_CLK		0x0154
+
+#define CCM_AHB_GATING_USB0	(1 << 0)
+#define CCM_AHB_GATING_EHCI1	(1 << 3)
+
+#define CCM_USB_PHY		(1 << 8)
+#define CCM_USB0_RESET		(1 << 0)
+#define CCM_USB1_RESET		(1 << 1)
+#define CCM_USB2_RESET		(1 << 2)
+
+int a10_clk_usb_activate(void);
+int a10_clk_usb_deactivate(void);
+
+#endif /* _A10_CLK_H_ */
diff --git a/sys/arm/allwinner/a10_ehci.c b/sys/arm/allwinner/a10_ehci.c
new file mode 100644
index 0000000..d3a90d0
--- /dev/null
+++ b/sys/arm/allwinner/a10_ehci.c
@@ -0,0 +1,279 @@
+/*-
+ * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Allwinner A10 attachment driver for the USB Enhanced Host Controller.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "opt_bus.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/condvar.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+#include <dev/ofw/ofw_bus.h> 
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/usb/usb.h> 
+#include <dev/usb/usbdi.h>
+
+#include <dev/usb/usb_core.h>
+#include <dev/usb/usb_busdma.h>
+#include <dev/usb/usb_process.h>
+#include <dev/usb/usb_util.h>
+
+#include <dev/usb/usb_controller.h>
+#include <dev/usb/usb_bus.h>
+#include <dev/usb/controller/ehci.h>
+#include <dev/usb/controller/ehcireg.h>
+
+#include "a10_clk.h"
+
+#define EHCI_HC_DEVSTR			"Allwinner Integrated USB 2.0 controller"
+
+#define SW_USB_PMU_IRQ_ENABLE		0x800
+
+#define SW_SDRAM_REG_HPCR_USB1		(0x250 + ((1 << 2) * 4))
+#define SW_SDRAM_REG_HPCR_USB2		(0x250 + ((1 << 2) * 5))
+#define SW_SDRAM_BP_HPCR_ACCESS		(1 << 0)
+
+#define SW_ULPI_BYPASS			(1 << 0)
+#define SW_AHB_INCRX_ALIGN		(1 << 8)
+#define	SW_AHB_INCR4			(1 << 9)
+#define SW_AHB_INCR8			(1 << 10)
+
+#define A10_READ_4(sc, reg)		\
+	bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
+
+#define A10_WRITE_4(sc, reg, data)	\
+	bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
+
+static device_attach_t a10_ehci_attach;
+static device_detach_t a10_ehci_detach;
+
+bs_r_1_proto(reversed);
+bs_w_1_proto(reversed);
+
+static int
+a10_ehci_probe(device_t self)
+{
+	if (!ofw_bus_is_compatible(self, "allwinner,usb-ehci")) 
+		return (ENXIO);
+
+	device_set_desc(self, EHCI_HC_DEVSTR);
+
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+a10_ehci_attach(device_t self)
+{
+	ehci_softc_t *sc = device_get_softc(self);
+	bus_space_handle_t bsh;
+	int err;
+	int rid;
+	uint32_t reg_value = 0;
+
+	/* initialise some bus fields */
+	sc->sc_bus.parent = self;
+	sc->sc_bus.devices = sc->sc_devices;
+	sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
+
+	/* get all DMA memory */
+	if (usb_bus_mem_alloc_all(&sc->sc_bus,
+	    USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
+		return (ENOMEM);
+	}
+
+	sc->sc_bus.usbrev = USB_REV_2_0;
+
+	rid = 0;
+	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (!sc->sc_io_res) {
+		device_printf(self, "Could not map memory\n");
+		goto error;
+	}
+
+	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
+	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
+	bsh = rman_get_bushandle(sc->sc_io_res);
+
+	sc->sc_io_size = rman_get_size(sc->sc_io_res);
+
+	if (bus_space_subregion(sc->sc_io_tag, bsh, 0x00,
+	    sc->sc_io_size, &sc->sc_io_hdl) != 0)
+		panic("%s: unable to subregion USB host registers",
+		    device_get_name(self));
+
+	rid = 0;
+	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
+	    RF_SHAREABLE | RF_ACTIVE);
+	if (sc->sc_irq_res == NULL) {
+		device_printf(self, "Could not allocate irq\n");
+		goto error;
+	}
+	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
+	if (!sc->sc_bus.bdev) {
+		device_printf(self, "Could not add USB device\n");
+		goto error;
+	}
+	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
+	device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
+
+	sprintf(sc->sc_vendor, "Allwinner");
+
+	err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
+	    NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
+	if (err) {
+		device_printf(self, "Could not setup irq, %d\n", err);
+		sc->sc_intr_hdl = NULL;
+		goto error;
+	}
+
+	sc->sc_flags |= EHCI_SCFLG_DONTRESET;
+
+	/* Enable clock for USB */
+	a10_clk_usb_activate();
+
+	/* Enable passby */
+	reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
+	reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */
+	reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */
+	reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */
+	reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */
+	A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
+
+	/* Configure port */
+	reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
+	reg_value |= SW_SDRAM_BP_HPCR_ACCESS;
+	A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
+
+	err = ehci_init(sc);
+	if (!err) {
+		err = device_probe_and_attach(sc->sc_bus.bdev);
+	}
+	if (err) {
+		device_printf(self, "USB init failed err=%d\n", err);
+		goto error;
+	}
+	return (0);
+
+error:
+	a10_ehci_detach(self);
+	return (ENXIO);
+}
+
+static int
+a10_ehci_detach(device_t self)
+{
+	ehci_softc_t *sc = device_get_softc(self);
+	device_t bdev;
+	int err;
+	uint32_t reg_value = 0;
+
+	if (sc->sc_bus.bdev) {
+		bdev = sc->sc_bus.bdev;
+		device_detach(bdev);
+		device_delete_child(self, bdev);
+	}
+	/* during module unload there are lots of children leftover */
+	device_delete_children(self);
+
+	if (sc->sc_irq_res && sc->sc_intr_hdl) {
+		/*
+		 * only call ehci_detach() after ehci_init()
+		 */
+		ehci_detach(sc);
+
+		err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
+
+		if (err)
+			/* XXX or should we panic? */
+			device_printf(self, "Could not tear down irq, %d\n",
+			    err);
+		sc->sc_intr_hdl = NULL;
+	}
+
+	if (sc->sc_irq_res) {
+		bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
+		sc->sc_irq_res = NULL;
+	}
+	if (sc->sc_io_res) {
+		bus_release_resource(self, SYS_RES_MEMORY, 0,
+		    sc->sc_io_res);
+		sc->sc_io_res = NULL;
+	}
+	usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
+
+	/* Disable configure port */
+	reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
+	reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS;
+	A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
+
+	/* Disable passby */
+	reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
+	reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */
+	reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */
+	reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */
+	reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */
+	A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
+
+	/* Disable clock for USB */
+	a10_clk_usb_deactivate();
+
+	return (0);
+}
+
+static device_method_t ehci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe, a10_ehci_probe),
+	DEVMETHOD(device_attach, a10_ehci_attach),
+	DEVMETHOD(device_detach, a10_ehci_detach),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+	DEVMETHOD_END
+};
+
+static driver_t ehci_driver = {
+	.name = "ehci",
+	.methods = ehci_methods,
+	.size = sizeof(ehci_softc_t),
+};
+
+static devclass_t ehci_devclass;
+
+DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0);
+MODULE_DEPEND(ehci, usb, 1, 1, 1);
diff --git a/sys/arm/allwinner/files.a10 b/sys/arm/allwinner/files.a10
index cb712d1..9d056fc 100644
--- a/sys/arm/allwinner/files.a10
+++ b/sys/arm/allwinner/files.a10
@@ -9,6 +9,8 @@ arm/arm/cpufunc_asm_arm11.S		standard
 arm/arm/cpufunc_asm_armv7.S		standard
 arm/arm/irq_dispatch.S			standard
 
+arm/allwinner/a10_clk.c			standard
+arm/allwinner/a10_ehci.c		optional	ehci
 arm/allwinner/timer.c			standard
 arm/allwinner/aintc.c			standard
 arm/allwinner/bus_space.c		standard