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authoralc <alc@FreeBSD.org>1999-07-03 06:33:48 +0000
committeralc <alc@FreeBSD.org>1999-07-03 06:33:48 +0000
commit29ea153b133f29de1f76c8f87cdb0aa6300f6813 (patch)
treef3a4cc0523e80c037532c075fb287d8c3ab46eb5 /sys/amd64
parentb6270032c16f447c90a1390dfde49f9918a6e2bc (diff)
downloadFreeBSD-src-29ea153b133f29de1f76c8f87cdb0aa6300f6813.zip
FreeBSD-src-29ea153b133f29de1f76c8f87cdb0aa6300f6813.tar.gz
An SMP-specific change: Add the lock prefix to RMW operations
on ipending.
Diffstat (limited to 'sys/amd64')
-rw-r--r--sys/amd64/amd64/apic_vector.S10
-rw-r--r--sys/amd64/amd64/cpu_switch.S4
-rw-r--r--sys/amd64/amd64/swtch.s4
3 files changed, 13 insertions, 5 deletions
diff --git a/sys/amd64/amd64/apic_vector.S b/sys/amd64/amd64/apic_vector.S
index 09e1b87..7acd37c 100644
--- a/sys/amd64/amd64/apic_vector.S
+++ b/sys/amd64/amd64/apic_vector.S
@@ -1,6 +1,6 @@
/*
* from: vector.s, 386BSD 0.1 unknown origin
- * $Id: apic_vector.s,v 1.39 1999/06/01 18:20:11 jlemon Exp $
+ * $Id: apic_vector.s,v 1.40 1999/06/16 03:53:52 tegge Exp $
*/
@@ -398,6 +398,7 @@ __CONCAT(Xresume,irq_num): ; \
MASK_IRQ(irq_num) ; \
EOI_IRQ(irq_num) ; \
AVCPL_LOCK ; /* MP-safe */ \
+ lock ; \
orl $IRQ_BIT(irq_num), _ipending ; \
AVCPL_UNLOCK ; \
lock ; \
@@ -409,6 +410,7 @@ __CONCAT(Xresume,irq_num): ; \
ALIGN_TEXT ; \
2: ; /* masked by cpl|cml */ \
APIC_ITRACE(apic_itrace_masked, irq_num, APIC_ITRACE_MASKED) ; \
+ lock ; \
orl $IRQ_BIT(irq_num), _ipending ; \
AVCPL_UNLOCK ; \
DELOCK ; /* XXX this is going away... */ \
@@ -418,6 +420,7 @@ __CONCAT(Xresume,irq_num): ; \
3: ; /* other cpu has isr lock */ \
APIC_ITRACE(apic_itrace_noisrlock, irq_num, APIC_ITRACE_NOISRLOCK) ;\
AVCPL_LOCK ; /* MP-safe */ \
+ lock ; \
orl $IRQ_BIT(irq_num), _ipending ; \
testl $IRQ_BIT(irq_num), _cpl ; \
jne 4f ; /* this INT masked */ \
@@ -485,6 +488,7 @@ __CONCAT(Xresume,irq_num): ; \
pushl %eax ; \
orl _intr_mask + (irq_num) * 4, %eax ; \
movl %eax, _cpl ; \
+ lock ; \
andl $~IRQ_BIT(irq_num), _ipending ; \
AVCPL_UNLOCK ; \
; \
@@ -508,6 +512,7 @@ __CONCAT(Xresume,irq_num): ; \
MASK_IRQ(irq_num) ; \
EOI_IRQ(irq_num) ; \
AVCPL_LOCK ; /* MP-safe */ \
+ lock ; \
orl $IRQ_BIT(irq_num), _ipending ; \
AVCPL_UNLOCK ; \
lock ; \
@@ -518,6 +523,7 @@ __CONCAT(Xresume,irq_num): ; \
ALIGN_TEXT ; \
2: ; /* masked by cpl, leave iactive set */ \
APIC_ITRACE(apic_itrace_masked, irq_num, APIC_ITRACE_MASKED) ; \
+ lock ; \
orl $IRQ_BIT(irq_num), _ipending ; \
AVCPL_UNLOCK ; \
ISR_RELLOCK ; /* XXX this is going away... */ \
@@ -527,6 +533,7 @@ __CONCAT(Xresume,irq_num): ; \
3: ; /* other cpu has isr lock */ \
APIC_ITRACE(apic_itrace_noisrlock, irq_num, APIC_ITRACE_NOISRLOCK) ;\
AVCPL_LOCK ; /* MP-safe */ \
+ lock ; \
orl $IRQ_BIT(irq_num), _ipending ; \
testl $IRQ_BIT(irq_num), _cpl ; \
jne 4f ; /* this INT masked */ \
@@ -698,6 +705,7 @@ _Xcpuast:
movl _cpl, %eax
#endif
pushl %eax
+ lock
orl $SWI_AST_PENDING, _ipending
AVCPL_UNLOCK
lock
diff --git a/sys/amd64/amd64/cpu_switch.S b/sys/amd64/amd64/cpu_switch.S
index 7578618..428b0ae 100644
--- a/sys/amd64/amd64/cpu_switch.S
+++ b/sys/amd64/amd64/cpu_switch.S
@@ -33,7 +33,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: swtch.s,v 1.81 1999/05/12 21:38:45 luoqi Exp $
+ * $Id: swtch.s,v 1.82 1999/06/01 18:19:45 jlemon Exp $
*/
#include "npx.h"
@@ -311,7 +311,7 @@ _idle:
* XXX: we had damn well better be sure we had it before doing this!
*/
CPL_LOCK /* XXX */
- andl $~SWI_AST_MASK, _ipending /* XXX */
+ MPLOCKED andl $~SWI_AST_MASK, _ipending /* XXX */
movl $0, _cpl /* XXX Allow ASTs on other CPU */
CPL_UNLOCK /* XXX */
movl $FREE_LOCK, %eax
diff --git a/sys/amd64/amd64/swtch.s b/sys/amd64/amd64/swtch.s
index 7578618..428b0ae 100644
--- a/sys/amd64/amd64/swtch.s
+++ b/sys/amd64/amd64/swtch.s
@@ -33,7 +33,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: swtch.s,v 1.81 1999/05/12 21:38:45 luoqi Exp $
+ * $Id: swtch.s,v 1.82 1999/06/01 18:19:45 jlemon Exp $
*/
#include "npx.h"
@@ -311,7 +311,7 @@ _idle:
* XXX: we had damn well better be sure we had it before doing this!
*/
CPL_LOCK /* XXX */
- andl $~SWI_AST_MASK, _ipending /* XXX */
+ MPLOCKED andl $~SWI_AST_MASK, _ipending /* XXX */
movl $0, _cpl /* XXX Allow ASTs on other CPU */
CPL_UNLOCK /* XXX */
movl $FREE_LOCK, %eax
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