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author | jkoshy <jkoshy@FreeBSD.org> | 2008-11-09 17:37:54 +0000 |
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committer | jkoshy <jkoshy@FreeBSD.org> | 2008-11-09 17:37:54 +0000 |
commit | fdb59f927ee739bbda9db671e11bf83d5a3143f3 (patch) | |
tree | 9977abc62b812534217ab29faac7edc58cae0570 /sys/amd64 | |
parent | 957a6ed81ce56e8deae2eb8eb5082acf7bbfe234 (diff) | |
download | FreeBSD-src-fdb59f927ee739bbda9db671e11bf83d5a3143f3.zip FreeBSD-src-fdb59f927ee739bbda9db671e11bf83d5a3143f3.tar.gz |
- Separate PMC class dependent code from other kinds of machine
dependencies. A 'struct pmc_classdep' structure describes operations
on PMCs; 'struct pmc_mdep' contains one or more 'struct pmc_classdep'
structures depending on the CPU in question.
Inside PMC class dependent code, row indices are relative to the
PMCs supported by the PMC class; MI code in "hwpmc_mod.c" translates
global row indices before invoking class dependent operations.
- Augment the OP_GETCPUINFO request with the number of PMCs present
in a PMC class.
- Move code common to Intel CPUs to file "hwpmc_intel.c".
- Move TSC handling to file "hwpmc_tsc.c".
Diffstat (limited to 'sys/amd64')
-rw-r--r-- | sys/amd64/include/pmc_mdep.h | 35 |
1 files changed, 32 insertions, 3 deletions
diff --git a/sys/amd64/include/pmc_mdep.h b/sys/amd64/include/pmc_mdep.h index a11a82a..d4aea66 100644 --- a/sys/amd64/include/pmc_mdep.h +++ b/sys/amd64/include/pmc_mdep.h @@ -35,8 +35,34 @@ #ifndef _MACHINE_PMC_MDEP_H #define _MACHINE_PMC_MDEP_H 1 +#ifdef _KERNEL +struct pmc_mdep; +#endif + #include <dev/hwpmc/hwpmc_amd.h> #include <dev/hwpmc/hwpmc_piv.h> +#include <dev/hwpmc/hwpmc_tsc.h> + +/* + * Intel processors implementing V2 and later of the Intel performance + * measurement architecture have PMCs of the following classes: TSC, + * IAF and IAP. + */ +#define PMC_MDEP_CLASS_INDEX_TSC 0 +#define PMC_MDEP_CLASS_INDEX_K8 1 +#define PMC_MDEP_CLASS_INDEX_P4 1 +#define PMC_MDEP_CLASS_INDEX_IAF 1 +#define PMC_MDEP_CLASS_INDEX_IAP 2 + +/* + * On the amd64 platform we support the following PMCs. + * + * TSC The timestamp counter + * K8 AMD Athlon64 and Opteron PMCs in 64 bit mode. + * PIV Intel P4/HTT and P4/EMT64 + * IAP Intel Core/Core2/Atom CPUs in 64 bits mode. + * IAF Intel fixed-function PMCs in Core2 and later CPUs. + */ union pmc_md_op_pmcallocate { struct pmc_md_amd_op_pmcallocate pm_amd; @@ -55,8 +81,6 @@ union pmc_md_pmc { struct pmc_md_p4_pmc pm_p4; }; -struct pmc; - #define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_rip) #define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_rbp) #define PMC_TRAPFRAME_TO_USER_SP(TF) ((TF)->tf_rsp) @@ -88,5 +112,10 @@ struct pmc; void start_exceptions(void), end_exceptions(void); void pmc_x86_lapic_enable_pmc_interrupt(void); -#endif +struct pmc_mdep *pmc_amd_initialize(void); +void pmc_amd_finalize(struct pmc_mdep *_md); +struct pmc_mdep *pmc_intel_initialize(void); +void pmc_intel_finalize(struct pmc_mdep *_md); + +#endif /* _KERNEL */ #endif /* _MACHINE_PMC_MDEP_H */ |