diff options
| author | alc <alc@FreeBSD.org> | 2010-03-21 00:13:11 +0000 |
|---|---|---|
| committer | alc <alc@FreeBSD.org> | 2010-03-21 00:13:11 +0000 |
| commit | 981be7060a50fc3283304bf2c4ab88ee9e679f6e (patch) | |
| tree | 1360a983c6502688b8cc951729675937b04b1bb3 /sys/amd64 | |
| parent | 2ee5d540fc032220b0c49219efe13687e3cd7c14 (diff) | |
| download | FreeBSD-src-981be7060a50fc3283304bf2c4ab88ee9e679f6e.zip FreeBSD-src-981be7060a50fc3283304bf2c4ab88ee9e679f6e.tar.gz | |
I am told by AMD that the machine check hardware on the instruction TLB
won't generate bogus exceptions. Therefore, the implementation of the
"unofficial" workaround needn't mask L1TP errors by the instruction cache
unit.
Diffstat (limited to 'sys/amd64')
| -rw-r--r-- | sys/amd64/amd64/mca.c | 11 | ||||
| -rw-r--r-- | sys/amd64/include/specialreg.h | 1 |
2 files changed, 4 insertions, 8 deletions
diff --git a/sys/amd64/amd64/mca.c b/sys/amd64/amd64/mca.c index ed55c2c..ccbab17 100644 --- a/sys/amd64/amd64/mca.c +++ b/sys/amd64/amd64/mca.c @@ -565,19 +565,16 @@ mca_init(void) /* * Disable logging of level one TLB parity (L1TP) errors by - * the data and instruction caches as an alternative - * workaround for AMD Family 10h Erratum 383. Unlike the - * recommended workaround, there is no performance penalty to - * this workaround. However, L1TP errors will go unreported. + * the data cache as an alternative workaround for AMD Family + * 10h Erratum 383. Unlike the recommended workaround, there + * is no performance penalty to this workaround. However, + * L1TP errors will go unreported. */ if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) { mask = rdmsr(MSR_MC0_CTL_MASK); if ((mask & (1UL << 5)) == 0) wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5)); - mask = rdmsr(MSR_MC1_CTL_MASK); - if ((mask & (1UL << 5)) == 0) - wrmsr(MSR_MC1_CTL_MASK, mask | (1UL << 5)); } for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) { /* By default enable logging of all errors. */ diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index baf2466..ed54f0d 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -507,7 +507,6 @@ #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ #define MSR_MC0_CTL_MASK 0xc0010044 -#define MSR_MC1_CTL_MASK 0xc0010045 /* VIA ACE crypto featureset: for via_feature_rng */ #define VIA_HAS_RNG 1 /* cpu has RNG */ |
