diff options
author | phk <phk@FreeBSD.org> | 1995-02-11 04:21:24 +0000 |
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committer | phk <phk@FreeBSD.org> | 1995-02-11 04:21:24 +0000 |
commit | 7f8d4b8663102109836d28a0ef1b806bf222b2c4 (patch) | |
tree | b6cd932a105ebe42f6dc29dfc4c12c418826d89e /sys/amd64 | |
parent | 5adebb03cd3b492bbbcc378c0e99a659f66a6e18 (diff) | |
download | FreeBSD-src-7f8d4b8663102109836d28a0ef1b806bf222b2c4.zip FreeBSD-src-7f8d4b8663102109836d28a0ef1b806bf222b2c4.tar.gz |
Intels App Note AP-485 applied.
We will now tell a good deal more about the CPU if Intel made it.
What is a i486DX2 Write-Back Enhanced CPU ?
Diffstat (limited to 'sys/amd64')
-rw-r--r-- | sys/amd64/amd64/locore.S | 13 | ||||
-rw-r--r-- | sys/amd64/amd64/locore.s | 13 | ||||
-rw-r--r-- | sys/amd64/amd64/machdep.c | 47 |
3 files changed, 61 insertions, 12 deletions
diff --git a/sys/amd64/amd64/locore.S b/sys/amd64/amd64/locore.S index 29870ac..167d9c5 100644 --- a/sys/amd64/amd64/locore.S +++ b/sys/amd64/amd64/locore.S @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * from: @(#)locore.s 7.3 (Berkeley) 5/13/91 - * $Id: locore.s,v 1.46 1995/01/14 13:20:07 bde Exp $ + * $Id: locore.s,v 1.47 1995/01/25 21:40:15 bde Exp $ */ /* @@ -121,9 +121,12 @@ tmpstk: .globl _boothowto,_bootdev .globl _cpu,_cold,_atdevbase,_cpu_vendor,_cpu_id,_bootinfo + .globl _cpu_high, _cpu_feature _cpu: .long 0 /* are we 386, 386sx, or 486 */ _cpu_id: .long 0 /* stepping ID */ +_cpu_high: .long 0 /* highest arg to CPUID */ +_cpu_feature: .long 0 /* features */ _cpu_vendor: .space 20 /* CPU origin code */ _bootinfo: .space BOOTINFO_SIZE /* bootinfo that we can handle */ _cold: .long 1 /* cold till we are not */ @@ -474,16 +477,18 @@ got_common_bi_size: 1: /* Use the `cpuid' instruction. */ xorl %eax,%eax - .byte 0x0f,0xa2 # cpuid 0 + .byte 0x0f,0xa2 # cpuid 0 + movl %eax,_cpu_high-KERNBASE # highest capability movl %ebx,_cpu_vendor-KERNBASE # store vendor string movl %edx,_cpu_vendor+4-KERNBASE movl %ecx,_cpu_vendor+8-KERNBASE movb $0,_cpu_vendor+12-KERNBASE movl $1,%eax - .byte 0x0f,0xa2 # cpuid 1 + .byte 0x0f,0xa2 # cpuid 1 movl %eax,_cpu_id-KERNBASE # store cpu_id - rorl $8,%eax # extract family type + movl %edx,_cpu_feature-KERNBASE # store cpu_feature + rorl $8,%eax # extract family type andl $15,%eax cmpl $5,%eax jae 1f diff --git a/sys/amd64/amd64/locore.s b/sys/amd64/amd64/locore.s index 29870ac..167d9c5 100644 --- a/sys/amd64/amd64/locore.s +++ b/sys/amd64/amd64/locore.s @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * from: @(#)locore.s 7.3 (Berkeley) 5/13/91 - * $Id: locore.s,v 1.46 1995/01/14 13:20:07 bde Exp $ + * $Id: locore.s,v 1.47 1995/01/25 21:40:15 bde Exp $ */ /* @@ -121,9 +121,12 @@ tmpstk: .globl _boothowto,_bootdev .globl _cpu,_cold,_atdevbase,_cpu_vendor,_cpu_id,_bootinfo + .globl _cpu_high, _cpu_feature _cpu: .long 0 /* are we 386, 386sx, or 486 */ _cpu_id: .long 0 /* stepping ID */ +_cpu_high: .long 0 /* highest arg to CPUID */ +_cpu_feature: .long 0 /* features */ _cpu_vendor: .space 20 /* CPU origin code */ _bootinfo: .space BOOTINFO_SIZE /* bootinfo that we can handle */ _cold: .long 1 /* cold till we are not */ @@ -474,16 +477,18 @@ got_common_bi_size: 1: /* Use the `cpuid' instruction. */ xorl %eax,%eax - .byte 0x0f,0xa2 # cpuid 0 + .byte 0x0f,0xa2 # cpuid 0 + movl %eax,_cpu_high-KERNBASE # highest capability movl %ebx,_cpu_vendor-KERNBASE # store vendor string movl %edx,_cpu_vendor+4-KERNBASE movl %ecx,_cpu_vendor+8-KERNBASE movb $0,_cpu_vendor+12-KERNBASE movl $1,%eax - .byte 0x0f,0xa2 # cpuid 1 + .byte 0x0f,0xa2 # cpuid 1 movl %eax,_cpu_id-KERNBASE # store cpu_id - rorl $8,%eax # extract family type + movl %edx,_cpu_feature-KERNBASE # store cpu_feature + rorl $8,%eax # extract family type andl $15,%eax cmpl $5,%eax jae 1f diff --git a/sys/amd64/amd64/machdep.c b/sys/amd64/amd64/machdep.c index 9dc2a4d..ff2c188 100644 --- a/sys/amd64/amd64/machdep.c +++ b/sys/amd64/amd64/machdep.c @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 - * $Id: machdep.c,v 1.106 1995/02/10 07:17:46 davidg Exp $ + * $Id: machdep.c,v 1.107 1995/02/10 07:44:03 davidg Exp $ */ #include "npx.h" @@ -377,7 +377,7 @@ struct cpu_nameclass i386_cpus[] = { static void identifycpu() { - extern u_long cpu_id; + extern u_long cpu_id, cpu_high, cpu_feature; extern char cpu_vendor[]; printf("CPU: "); if (cpu >= 0 @@ -413,11 +413,50 @@ identifycpu() printf(" %d MHz", pentium_mhz); } #endif - if(cpu_id) - printf(" Id = 0x%lx",cpu_id); if(*cpu_vendor) printf(" Origin = \"%s\"",cpu_vendor); + if(cpu_id) + printf(" Id = 0x%lx",cpu_id); printf("\n"); /* cpu speed would be nice, but how? */ + if (!strcmp(cpu_vendor,"GenuineIntel")) { + printf(" This is a"); + if ((cpu_id & 0xf00) > 3) { + switch (cpu_id & 0x3000) { + case 0x1000: printf("Overdrive "); break; + case 0x2000: printf("Dual "); break; + } + if ((cpu_id & 0xf00) == 0x400) + printf("n i486"); + else if ((cpu_id & 0xf00) == 0x500) + printf(" Pentium "); + else + printf(" unknown CPU"); + switch (cpu_id & 0xff0) { + case 0x400: printf("DX"); break; + case 0x410: printf("DX"); break; + case 0x420: printf("SX"); break; + case 0x430: printf("DX2"); break; + case 0x440: printf("SL"); break; + case 0x450: printf("SX2"); break; + case 0x470: printf("DX2 Write-Back Enhanced"); + break; + case 0x480: printf("DX4"); break; + case 0x510: printf("510\\60 or 567\\66"); break; + case 0x520: printf("735\\90 or 815\\100"); break; + } + } + printf(" Stepping=%d", cpu_id & 0xf); + if (cpu_high > 0) { + printf(" Features=0x%lx",cpu_feature); + if (cpu_feature & 0x1) printf(" FPU"); + if (cpu_feature & 0x2) printf(" VME"); + if (cpu_feature & 0x8) printf(" PSE"); + if (cpu_feature & 0x80) printf(" MCE"); + if (cpu_feature & 0x100) printf(" CX8"); + if (cpu_feature & 0x200) printf(" APIC"); + } + printf("\n"); + } /* * Now that we have told the user what they have, |