Made PEND_INTS default.

Made NEW_STRATEGY default.
Removed misc. old cruft.

Centralized simple locks into mp_machdep.c
Centralized simple lock macros into param.h

More cleanup in the direction of making splxx()/cpl MP-safe.

10 files changed, 163 insertions, 326 deletions

diff --git a/sys/amd64/amd64/apic_vector.S b/sys/amd64/amd64/apic_vector.S
index f2a8bce..9d1d4a0 100644
--- a/sys/amd64/amd64/apic_vector.S
+++ b/sys/amd64/amd64/apic_vector.S
@@ -1,12 +1,12 @@
 /*
  *	from: vector.s, 386BSD 0.1 unknown origin
- *	$Id: apic_vector.s,v 1.15 1997/08/10 20:58:57 fsmp Exp $
+ *	$Id: apic_vector.s,v 1.24 1997/08/21 04:52:30 smp Exp smp $
  */
 
 
 #include <machine/apic.h>
 #include <machine/smp.h>
-#include <machine/smptests.h>		/** PEND_INTS, various counters */
+#include <machine/smptests.h>			/** various things... */
 
 #include "i386/isa/intr_machdep.h"
 
@@ -27,6 +27,7 @@
 
 #define GET_FAST_INTR_LOCK						\
 	call	_get_isrlock
+
 #define REL_FAST_INTR_LOCK						\
 	pushl	$_mp_lock ;	/* GIANT_LOCK */			\
 	call	_MPrellock ;						\
@@ -34,11 +35,6 @@
 
 #endif /* FAST_SIMPLELOCK */
 
-#define REL_ISR_LOCK							\
-	pushl	$_mp_lock ;	/* GIANT_LOCK */			\
-	call	_MPrellock ;						\
-	add	$4, %esp
-
 /* convert an absolute IRQ# into a bitmask */
 #define IRQ_BIT(irq_num)	(1 << (irq_num))
 
@@ -47,105 +43,13 @@
 
 
 /*
- * 'lazy masking' code suggested by Bruce Evans <bde@zeta.org.au>
- */
-
-#ifdef PEND_INTS
-
-/*
- * the 1st version fails because masked edge-triggered INTs are lost
- * by the IO APIC.  This version tests to see whether we are handling
- * an edge or level triggered INT.  Level-triggered INTs must still be
- * masked as we don't clear the source, and the EOI cycle would allow
- * recursive INTs to occur.
- */
-#define MAYBE_MASK_IRQ(irq_num)						\
-	lock ;					/* MP-safe */		\
-	btsl	$(irq_num),iactive ;		/* lazy masking */	\
-	jc	6f ;				/* already active */	\
-	pushl	$_mp_lock ;			/* GIANT_LOCK */	\
-	call	_MPtrylock ;			/* try to get lock */	\
-	add $4,	%esp ;							\
-	testl	%eax, %eax ;			/* did we get it? */	\
-	jnz	8f ;				/* yes, enter kernel */	\
-6: ;						/* active or locked */	\
-	IMASK_LOCK ;				/* into critical reg */	\
-	testl	$IRQ_BIT(irq_num),_apic_pin_trigger ;			\
-	jz	7f ;				/* edge, don't mask */	\
-	orl	$IRQ_BIT(irq_num),_apic_imen ;	/* set the mask bit */	\
-	movl	_ioapic,%ecx ;			/* ioapic[0] addr */	\
-	movl	$REDTBL_IDX(irq_num),(%ecx) ;	/* write the index */	\
-	movl	IOAPIC_WINDOW(%ecx),%eax ;	/* current value */	\
-	orl	$IOART_INTMASK,%eax ;		/* set the mask */	\
-	movl	%eax,IOAPIC_WINDOW(%ecx) ;	/* new value */		\
-7: ;									\
-	lock ;					/* MP-safe */		\
-	orl	$IRQ_BIT(irq_num), _ipending ;	/* set _ipending bit */	\
-	IMASK_UNLOCK ;				/* exit critical reg */	\
-	movl	$0, lapic_eoi ;			/* do the EOI */	\
-	popl	%es ;							\
-	popl	%ds ;							\
-	popal ;								\
-	addl	$4+4,%esp ;						\
-	iret ;								\
-;									\
-	ALIGN_TEXT ;							\
-8:
-
-#else /* PEND_INTS */
-
-#define MAYBE_MASK_IRQ(irq_num)						\
-	lock ;					/* MP-safe */		\
-	btsl	$(irq_num),iactive ;		/* lazy masking */	\
-	jnc	1f ;				/* NOT active */	\
-	IMASK_LOCK ;				/* enter critical reg */\
-	orl	$IRQ_BIT(irq_num),_apic_imen ;	/* set the mask bit */	\
-	movl	_ioapic,%ecx ;			/* ioapic[0]addr */	\
-	movl	$REDTBL_IDX(irq_num),(%ecx) ;	/* write the index */	\
-	movl	IOAPIC_WINDOW(%ecx),%eax ;	/* current value */	\
-	orl	$IOART_INTMASK,%eax ;		/* set the mask */	\
-	movl	%eax,IOAPIC_WINDOW(%ecx) ;	/* new value */		\
-	lock ;					/* MP-safe */		\
-	orl	$IRQ_BIT(irq_num), _ipending ;	/* set _ipending bit */	\
-	movl	$0, lapic_eoi ;			/* do the EOI */	\
-	IMASK_UNLOCK ;				/* exit critical reg */	\
-	popl	%es ;							\
-	popl	%ds ;							\
-	popal ;								\
-	addl	$4+4,%esp ;						\
-	iret ;								\
-;									\
-	ALIGN_TEXT ;							\
-1: ;									\
-	call	_get_mplock			/* SMP Spin lock */
-
-#endif /* PEND_INTS */
-
-
-#define MAYBE_UNMASK_IRQ(irq_num)					\
-	cli ;	/* must unmask _apic_imen and IO APIC atomically */	\
-	lock ;					/* MP-safe */		\
-	andl	$~IRQ_BIT(irq_num),iactive ;				\
-	IMASK_LOCK ;				/* enter critical reg */\
-	testl	$IRQ_BIT(irq_num),_apic_imen ;				\
-	je	9f ;							\
-	andl	$~IRQ_BIT(irq_num),_apic_imen ;	/* clear mask bit */	\
-	movl	_ioapic,%ecx ;			/* ioapic[0]addr */	\
-	movl	$REDTBL_IDX(irq_num),(%ecx) ;	/* write the index */	\
-	movl	IOAPIC_WINDOW(%ecx),%eax ;	/* current value */	\
-	andl	$~IOART_INTMASK,%eax ;		/* clear the mask */	\
-	movl	%eax,IOAPIC_WINDOW(%ecx) ;	/* new value */		\
-9: ;									\
-	IMASK_UNLOCK ;				/* exit critical reg */	\
-	sti	/* XXX _doreti repeats the cli/sti */
-
-
-/*
  * Macros for interrupt interrupt entry, call to handler, and exit.
  */
 
 #ifdef FAST_WITHOUTCPL
 
+/*
+ */
 #define	FAST_INTR(irq_num, vec_name)					\
 	.text ;								\
 	SUPERALIGN_TEXT ;						\
@@ -244,51 +148,122 @@ IDTVEC(vec_name) ;							\
 #endif /** FAST_WITHOUTCPL */
 
 
-#define	INTR(irq_num, vec_name)						\
-	.text ;								\
-	SUPERALIGN_TEXT ;						\
-IDTVEC(vec_name) ;							\
+/*
+ * 
+ */
+#define PUSH_FRAME							\
 	pushl	$0 ;		/* dummy error code */			\
 	pushl	$0 ;		/* dummy trap type */			\
 	pushal ;							\
 	pushl	%ds ;		/* save data and extra segments ... */	\
-	pushl	%es ;							\
-	movl	$KDSEL,%eax ;	/* ... and reload with kernel's ... */	\
-	movl	%ax,%ds ;	/* ... early for obsolete reasons */	\
-	movl	%ax,%es ;						\
-	MAYBE_MASK_IRQ(irq_num) ;					\
-	movl	$0, lapic_eoi ;						\
-	movl	_cpl,%eax ;						\
-	testl	$IRQ_BIT(irq_num), %eax ;				\
-	jne	3f ;							\
+	pushl	%es
+
+#define POP_FRAME							\
+	popl	%es ;							\
+	popl	%ds ;							\
+	popal ;								\
+	addl	$4+4,%esp
+
+/*
+ * Test to see whether we are handling an edge or level triggered INT.
+ *  Level-triggered INTs must still be masked as we don't clear the source,
+ *  and the EOI cycle would cause redundant INTs to occur.
+ */
+#define MASK_LEVEL_IRQ(irq_num)						\
+	IMASK_LOCK ;				/* into critical reg */	\
+	testl	$IRQ_BIT(irq_num), _apic_pin_trigger ;			\
+	jz	8f ;				/* edge, don't mask */	\
+	orl	$IRQ_BIT(irq_num), _apic_imen ;	/* set the mask bit */	\
+	movl	_ioapic, %ecx ;			/* ioapic[0] addr */	\
+	movl	$REDTBL_IDX(irq_num), (%ecx) ;	/* write the index */	\
+	movl	IOAPIC_WINDOW(%ecx), %eax ;	/* current value */	\
+	orl	$IOART_INTMASK, %eax ;		/* set the mask */	\
+	movl	%eax, IOAPIC_WINDOW(%ecx) ;	/* new value */		\
+8: ;									\
+	IMASK_UNLOCK
+
+/*
+ * Test to see if the source is currntly masked, clear if so.
+ */
+#define UNMASK_IRQ(irq_num)					\
+	IMASK_LOCK ;				/* into critical reg */	\
+	testl	$IRQ_BIT(irq_num), _apic_imen ;				\
+	je	9f ;							\
+	andl	$~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */	\
+	movl	_ioapic,%ecx ;			/* ioapic[0]addr */	\
+	movl	$REDTBL_IDX(irq_num),(%ecx) ;	/* write the index */	\
+	movl	IOAPIC_WINDOW(%ecx),%eax ;	/* current value */	\
+	andl	$~IOART_INTMASK,%eax ;		/* clear the mask */	\
+	movl	%eax,IOAPIC_WINDOW(%ecx) ;	/* new value */		\
+9: ;									\
+	IMASK_UNLOCK
+
+#define	INTR(irq_num, vec_name)						\
+	.text ;								\
+	SUPERALIGN_TEXT ;						\
+IDTVEC(vec_name) ;							\
+	PUSH_FRAME ;							\
+	movl	$KDSEL, %eax ;	/* reload with kernel's data segment */	\
+	movl	%ax, %ds ;						\
+	movl	%ax, %es ;						\
+;									\
+	lock ;					/* MP-safe */		\
+	btsl	$(irq_num), iactive ;		/* lazy masking */	\
+	jc	1f ;				/* already active */	\
+;									\
+	ISR_TRYLOCK ;		/* XXX this is going away... */		\
+	testl	%eax, %eax ;			/* did we get it? */	\
+	jz	1f ;				/* no */		\
+;									\
+	CPL_LOCK ;				/* MP-safe */		\
+	testl	$IRQ_BIT(irq_num), _cpl ;				\
+	jne	2f ;							\
+	orl	$IRQ_BIT(irq_num), _cil ;				\
+	CPL_UNLOCK ;							\
+;									\
+	movl	$0, lapic_eoi ;			/* XXX too soon? */	\
 	incb	_intr_nesting_level ;					\
 __CONCAT(Xresume,irq_num): ;						\
-	FAKE_MCOUNT(12*4(%esp)) ;	/* XXX late to avoid dbl cnt */ \
-	incl	_cnt+V_INTR ;	/* tally interrupts */			\
-	movl	_intr_countp + (irq_num) * 4,%eax ;			\
-	incl	(%eax) ;						\
-	movl	_cpl,%eax ;						\
+	FAKE_MCOUNT(12*4(%esp)) ;		/* XXX avoid dbl cnt */ \
+	lock ;	incl	_cnt+V_INTR ;		/* tally interrupts */	\
+	movl	_intr_countp + (irq_num) * 4, %eax ;			\
+	lock ;	incl	(%eax) ;					\
+;									\
+	CPL_LOCK ;				/* MP-safe */		\
+	movl	_cpl, %eax ;						\
 	pushl	%eax ;							\
+	orl	_intr_mask + (irq_num) * 4, %eax ;			\
+	movl	%eax, _cpl ;						\
+	CPL_UNLOCK ;							\
+;									\
 	pushl	_intr_unit + (irq_num) * 4 ;				\
-	orl	_intr_mask + (irq_num) * 4,%eax ;			\
-	movl	%eax,_cpl ;						\
 	sti ;								\
 	call	*_intr_handler + (irq_num) * 4 ;			\
-	MAYBE_UNMASK_IRQ(irq_num) ;					\
+	cli ;								\
+;									\
+	lock ;	andl	$~IRQ_BIT(irq_num), iactive ;			\
+	UNMASK_IRQ(irq_num) ;						\
+	sti ;				/* doreti repeats cli/sti */	\
 	MEXITCOUNT ;							\
 	jmp	_doreti ;						\
 ;									\
 	ALIGN_TEXT ;							\
-3: ;									\
-	/* XXX skip mcounting here to avoid double count */		\
-	lock ;					/* MP-safe */		\
+1: ;						/* active or locked */	\
+	MASK_LEVEL_IRQ(irq_num) ;					\
+	movl	$0, lapic_eoi ;			/* do the EOI */	\
+;									\
+	CPL_LOCK ;				/* MP-safe */		\
 	orl	$IRQ_BIT(irq_num), _ipending ;				\
-	REL_ISR_LOCK ;							\
-	popl	%es ;							\
-	popl	%ds ;							\
-	popal ;								\
-	addl	$4+4,%esp ;						\
-	iret
+	CPL_UNLOCK ;							\
+;									\
+	POP_FRAME ;							\
+	iret ;								\
+;									\
+	ALIGN_TEXT ;							\
+2: ;						/* masked by cpl */	\
+	CPL_UNLOCK ;							\
+	ISR_RELLOCK ;		/* XXX this is going away... */		\
+	jmp	1b
 
 
 /*
@@ -302,10 +277,6 @@ __CONCAT(Xresume,irq_num): ;						\
 	SUPERALIGN_TEXT
 	.globl _Xspuriousint
 _Xspuriousint:
-#ifdef COUNT_SPURIOUS_INTS
-	ss
-	incl	_sihits
-#endif
 
 	/* No EOI cycle used here */
 
@@ -358,10 +329,6 @@ _Xcpustop:
 
 	movl	_cpuid, %eax
 
-#ifdef COUNT_CSHITS
-	incl	_cshits(,%eax,4)
-#endif /* COUNT_CSHITS */
-
 	ASMPOSTCODE_HI(0x1)
 
 	lock
@@ -470,12 +437,6 @@ _ivectors:
 iactive:
 	.long	0
 
-#ifdef COUNT_SPURIOUS_INTS
-	.globl	_sihits
-_sihits:
-	.long	0
-#endif /* COUNT_SPURIOUS_INTS */
-
 #ifdef COUNT_XINVLTLB_HITS
 	.globl	_xhits
 _xhits:
@@ -489,17 +450,9 @@ _stopped_cpus:
 _started_cpus:
 	.long	0
 
-#ifdef COUNT_CSHITS
-	.globl	_cshits
-_cshits:
-	.space	(NCPU * 4), 0
-#endif /* COUNT_CSHITS */
-
-#ifdef PEND_INTS
 	.globl	_apic_pin_trigger
 _apic_pin_trigger:
 	.space	(NAPIC * 4), 0
-#endif /* PEND_INTS */
 
 
 /*
diff --git a/sys/amd64/amd64/exception.S b/sys/amd64/amd64/exception.S
index 09635fa..67bf676 100644
--- a/sys/amd64/amd64/exception.S
+++ b/sys/amd64/amd64/exception.S
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: exception.s,v 1.38 1997/08/10 21:18:01 fsmp Exp $
+ *	$Id: exception.s,v 1.12 1997/08/21 04:53:27 smp Exp smp $
  */
 
 #include "npx.h"				/* NNPX */
@@ -39,48 +39,7 @@
 #include <machine/psl.h>			/* PSL_I */
 #include <machine/trap.h>			/* trap codes */
 #include <machine/asmacros.h>			/* miscellaneous macros */
-
-#ifdef SMP
-
-#define	MPLOCKED	lock ;
-
-#define FPU_LOCK	call	_get_fpu_lock
-#define ALIGN_LOCK	call	_get_align_lock
-#define SYSCALL_LOCK	call	_get_syscall_lock
-#define ALTSYSCALL_LOCK	call	_get_altsyscall_lock
-
-/* protects the IO APIC and apic_imen as a critical region */
-#define IMASK_LOCK							\
-	pushl	$_imen_lock ;			/* address of lock */	\
-	call	_s_lock ;			/* MP-safe */		\
-	addl	$4,%esp
-
-#define IMASK_UNLOCK							\
-	pushl	$_imen_lock ;			/* address of lock */	\
-	call	_s_unlock ;			/* MP-safe */		\
-	addl	$4,%esp
-
-/* protects cpl updates as a critical region */
-#define CPL_LOCK							\
-	pushl	$_cpl_lock ;			/* address of lock */	\
-	call	_s_lock ;			/* MP-safe */		\
-	addl	$4,%esp
-
-#define CPL_UNLOCK							\
-	pushl	$_cpl_lock ;			/* address of lock */	\
-	call	_s_unlock ;			/* MP-safe */		\
-	addl	$4,%esp
-
-#else  /* SMP */
-
-#define	MPLOCKED				/* NOP */
-
-#define FPU_LOCK				/* NOP */
-#define ALIGN_LOCK				/* NOP */
-#define SYSCALL_LOCK				/* NOP */
-#define ALTSYSCALL_LOCK				/* NOP */
-
-#endif  /* SMP */
+#include <machine/param.h>
 
 #define	KCSEL		0x08			/* kernel code selector */
 #define	KDSEL		0x10			/* kernel data selector */
diff --git a/sys/amd64/amd64/exception.s b/sys/amd64/amd64/exception.s
index 09635fa..67bf676 100644
--- a/sys/amd64/amd64/exception.s
+++ b/sys/amd64/amd64/exception.s
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: exception.s,v 1.38 1997/08/10 21:18:01 fsmp Exp $
+ *	$Id: exception.s,v 1.12 1997/08/21 04:53:27 smp Exp smp $
  */
 
 #include "npx.h"				/* NNPX */
@@ -39,48 +39,7 @@
 #include <machine/psl.h>			/* PSL_I */
 #include <machine/trap.h>			/* trap codes */
 #include <machine/asmacros.h>			/* miscellaneous macros */
-
-#ifdef SMP
-
-#define	MPLOCKED	lock ;
-
-#define FPU_LOCK	call	_get_fpu_lock
-#define ALIGN_LOCK	call	_get_align_lock
-#define SYSCALL_LOCK	call	_get_syscall_lock
-#define ALTSYSCALL_LOCK	call	_get_altsyscall_lock
-
-/* protects the IO APIC and apic_imen as a critical region */
-#define IMASK_LOCK							\
-	pushl	$_imen_lock ;			/* address of lock */	\
-	call	_s_lock ;			/* MP-safe */		\
-	addl	$4,%esp
-
-#define IMASK_UNLOCK							\
-	pushl	$_imen_lock ;			/* address of lock */	\
-	call	_s_unlock ;			/* MP-safe */		\
-	addl	$4,%esp
-
-/* protects cpl updates as a critical region */
-#define CPL_LOCK							\
-	pushl	$_cpl_lock ;			/* address of lock */	\
-	call	_s_lock ;			/* MP-safe */		\
-	addl	$4,%esp
-
-#define CPL_UNLOCK							\
-	pushl	$_cpl_lock ;			/* address of lock */	\
-	call	_s_unlock ;			/* MP-safe */		\
-	addl	$4,%esp
-
-#else  /* SMP */
-
-#define	MPLOCKED				/* NOP */
-
-#define FPU_LOCK				/* NOP */
-#define ALIGN_LOCK				/* NOP */
-#define SYSCALL_LOCK				/* NOP */
-#define ALTSYSCALL_LOCK				/* NOP */
-
-#endif  /* SMP */
+#include <machine/param.h>
 
 #define	KCSEL		0x08			/* kernel code selector */
 #define	KDSEL		0x10			/* kernel data selector */
diff --git a/sys/amd64/amd64/mp_machdep.c b/sys/amd64/amd64/mp_machdep.c
index e5fb310..b02fde7 100644
--- a/sys/amd64/amd64/mp_machdep.c
+++ b/sys/amd64/amd64/mp_machdep.c
@@ -22,7 +22,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: mp_machdep.c,v 1.41 1997/08/10 19:32:38 fsmp Exp $
+ *	$Id: mp_machdep.c,v 1.29 1997/08/21 04:53:27 smp Exp smp $
  */
 
 #include "opt_smp.h"
@@ -1419,6 +1419,18 @@ default_mp_table(int type)
  * initialize all the SMP locks
  */
 
+/* critical region around IO APIC, apic_imen */
+struct simplelock	imen_lock;
+
+/* critical region around splxx(), cpl, cil, ipending */
+struct simplelock	cpl_lock;
+
+/* Make FAST_INTR() routines sequential */
+struct simplelock	fast_intr_lock;
+
+/* critical region around INTR() routines */
+struct simplelock	intr_lock;
+
 /* lock the com (tty) data structures */
 struct simplelock	com_lock;
 
diff --git a/sys/amd64/amd64/mptable.c b/sys/amd64/amd64/mptable.c
index e5fb310..b02fde7 100644
--- a/sys/amd64/amd64/mptable.c
+++ b/sys/amd64/amd64/mptable.c
@@ -22,7 +22,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: mp_machdep.c,v 1.41 1997/08/10 19:32:38 fsmp Exp $
+ *	$Id: mp_machdep.c,v 1.29 1997/08/21 04:53:27 smp Exp smp $
  */
 
 #include "opt_smp.h"
@@ -1419,6 +1419,18 @@ default_mp_table(int type)
  * initialize all the SMP locks
  */
 
+/* critical region around IO APIC, apic_imen */
+struct simplelock	imen_lock;
+
+/* critical region around splxx(), cpl, cil, ipending */
+struct simplelock	cpl_lock;
+
+/* Make FAST_INTR() routines sequential */
+struct simplelock	fast_intr_lock;
+
+/* critical region around INTR() routines */
+struct simplelock	intr_lock;
+
 /* lock the com (tty) data structures */
 struct simplelock	com_lock;
 
diff --git a/sys/amd64/amd64/tsc.c b/sys/amd64/amd64/tsc.c
index 5b54178..7f89a7f 100644
--- a/sys/amd64/amd64/tsc.c
+++ b/sys/amd64/amd64/tsc.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
- *	$Id: clock.c,v 1.97 1997/07/22 20:12:04 fsmp Exp $
+ *	$Id: clock.c,v 1.8 1997/08/21 04:51:12 smp Exp smp $
  */
 
 /*
@@ -66,7 +66,6 @@
 #include <machine/ipl.h>
 #ifdef APIC_IO
 #include <machine/smp.h>
-#include <machine/smptests.h>		/** NEW_STRATEGY (,SMP_TIMER_NC) */
 #endif /* APIC_IO */
 
 #include <i386/isa/icu.h>
@@ -74,6 +73,9 @@
 #include <i386/isa/rtc.h>
 #include <i386/isa/timerreg.h>
 
+#include <i386/isa/intr_machdep.h>
+#include <sys/interrupt.h>
+
 /*
  * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
  * can use a simple formula for leap years.
@@ -859,11 +861,6 @@ cpu_initclocks()
 	/* Finish initializing 8253 timer 0. */
 #ifdef APIC_IO
 
-#ifdef NEW_STRATEGY
-#ifdef SMP_TIMER_NC
-#error 'options SMP_TIMER_NC' no longer used, remove & reconfig.
-#endif	/** XXX SMP_TIMER_NC */
-
 	/* 1st look for ExtInt on pin 0 */
 	if (apic_int_type(0, 0) == 3) {
 		/*
@@ -897,33 +894,6 @@ cpu_initclocks()
 	else 
 		panic("neither pin 0 or pin 2 works for 8254");
 
-#else /** NEW_STRATEGY */
-
-	/* 8254 is traditionally on ISA IRQ0 */
-#if defined(SMP_TIMER_NC)
-	x = -1;
-#else
-	x = isa_apic_pin(0);
-#endif	/** XXX SMP_TIMER_NC */
-
-	if (x < 0) {
-		/* bummer, attempt to redirect thru the 8259 */
-		if (bootverbose)
-			printf("APIC missing 8254 connection\n");
-
-		/* allow 8254 timer to INTerrupt 8259 */
-		x = inb(IO_ICU1 + 1);		/* current mask in 8259 */
-		x &= ~1;			/* clear 8254 timer mask */
-		outb(IO_ICU1 + 1, x);		/* write new mask */
-
-		/* program IO APIC for type 3 INT on INT0 */
-		if (ext_int_setup(0, 0) < 0)
-			panic("8254 redirect impossible!");
-		x = 0;				/* 8259 is on 0 */
-	}
-
-#endif /** NEW_STRATEGY */
-
 	/* setup the vectors */
 	vec[x] = (u_int)vec8254;
 	Xintr8254 = (u_int)ivectors[x];
@@ -966,9 +936,11 @@ cpu_initclocks()
 	if (isa_apic_pin(8) != 8)
 		panic("APIC RTC != 8");
 #endif /* APIC_IO */
+
 	register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0,
 		      /* XXX */ (inthand2_t *)rtcintr, &stat_imask,
 		      /* unit */ 0);
+
 #ifdef APIC_IO
 	INTREN(APIC_IRQ8);
 #else
diff --git a/sys/amd64/include/mptable.h b/sys/amd64/include/mptable.h
index e5fb310..b02fde7 100644
--- a/sys/amd64/include/mptable.h
+++ b/sys/amd64/include/mptable.h
@@ -22,7 +22,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: mp_machdep.c,v 1.41 1997/08/10 19:32:38 fsmp Exp $
+ *	$Id: mp_machdep.c,v 1.29 1997/08/21 04:53:27 smp Exp smp $
  */
 
 #include "opt_smp.h"
@@ -1419,6 +1419,18 @@ default_mp_table(int type)
  * initialize all the SMP locks
  */
 
+/* critical region around IO APIC, apic_imen */
+struct simplelock	imen_lock;
+
+/* critical region around splxx(), cpl, cil, ipending */
+struct simplelock	cpl_lock;
+
+/* Make FAST_INTR() routines sequential */
+struct simplelock	fast_intr_lock;
+
+/* critical region around INTR() routines */
+struct simplelock	intr_lock;
+
 /* lock the com (tty) data structures */
 struct simplelock	com_lock;
 
diff --git a/sys/amd64/include/smp.h b/sys/amd64/include/smp.h
index e80d91a..6b195f6f 100644
--- a/sys/amd64/include/smp.h
+++ b/sys/amd64/include/smp.h
@@ -6,7 +6,7 @@
  * this stuff is worth it, you can buy me a beer in return.   Poul-Henning Kamp
  * ----------------------------------------------------------------------------
  *
- * $Id: smp.h,v 1.26 1997/08/18 03:35:59 fsmp Exp $
+ * $Id: smp.h,v 1.23 1997/08/21 04:48:45 smp Exp smp $
  *
  */
 
@@ -75,10 +75,6 @@ extern volatile u_int		started_cpus;
 extern u_int			vec[];
 extern u_int			Xintr8254;
 extern u_int			mask8254;
-extern struct simplelock	imen_lock;
-extern struct simplelock	cpl_lock;
-extern struct simplelock	fast_intr_lock;
-extern struct simplelock	intr_lock;
 
 /* functions in apic_ipl.s */
 void	vec8254			__P((void));
@@ -88,13 +84,6 @@ void	apic_eoi		__P((void));
 u_int	io_apic_read		__P((int, int));
 void	io_apic_write		__P((int, int, u_int));
 
-/* functions in simplelock.s */
-#include <machine/param.h>
-void	s_lock_init		__P((struct simplelock *));
-void	s_lock			__P((struct simplelock *));
-int	s_lock_try		__P((struct simplelock *));
-void	s_unlock		__P((struct simplelock *));
-
 /* global data in mp_machdep.c */
 extern int			mp_ncpus;
 extern int			mp_naps;
@@ -113,8 +102,6 @@ extern u_int			all_cpus;
 extern u_int			SMP_prvpt[];
 extern u_char			SMP_ioapic[];
 
-extern struct simplelock	com_lock;
-
 /* functions in mp_machdep.c */
 u_int	mp_bootaddress		__P((u_int));
 int	mp_probe		__P((void));
diff --git a/sys/amd64/isa/clock.c b/sys/amd64/isa/clock.c
index 5b54178..7f89a7f 100644
--- a/sys/amd64/isa/clock.c
+++ b/sys/amd64/isa/clock.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
- *	$Id: clock.c,v 1.97 1997/07/22 20:12:04 fsmp Exp $
+ *	$Id: clock.c,v 1.8 1997/08/21 04:51:12 smp Exp smp $
  */
 
 /*
@@ -66,7 +66,6 @@
 #include <machine/ipl.h>
 #ifdef APIC_IO
 #include <machine/smp.h>
-#include <machine/smptests.h>		/** NEW_STRATEGY (,SMP_TIMER_NC) */
 #endif /* APIC_IO */
 
 #include <i386/isa/icu.h>
@@ -74,6 +73,9 @@
 #include <i386/isa/rtc.h>
 #include <i386/isa/timerreg.h>
 
+#include <i386/isa/intr_machdep.h>
+#include <sys/interrupt.h>
+
 /*
  * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
  * can use a simple formula for leap years.
@@ -859,11 +861,6 @@ cpu_initclocks()
 	/* Finish initializing 8253 timer 0. */
 #ifdef APIC_IO
 
-#ifdef NEW_STRATEGY
-#ifdef SMP_TIMER_NC
-#error 'options SMP_TIMER_NC' no longer used, remove & reconfig.
-#endif	/** XXX SMP_TIMER_NC */
-
 	/* 1st look for ExtInt on pin 0 */
 	if (apic_int_type(0, 0) == 3) {
 		/*
@@ -897,33 +894,6 @@ cpu_initclocks()
 	else 
 		panic("neither pin 0 or pin 2 works for 8254");
 
-#else /** NEW_STRATEGY */
-
-	/* 8254 is traditionally on ISA IRQ0 */
-#if defined(SMP_TIMER_NC)
-	x = -1;
-#else
-	x = isa_apic_pin(0);
-#endif	/** XXX SMP_TIMER_NC */
-
-	if (x < 0) {
-		/* bummer, attempt to redirect thru the 8259 */
-		if (bootverbose)
-			printf("APIC missing 8254 connection\n");
-
-		/* allow 8254 timer to INTerrupt 8259 */
-		x = inb(IO_ICU1 + 1);		/* current mask in 8259 */
-		x &= ~1;			/* clear 8254 timer mask */
-		outb(IO_ICU1 + 1, x);		/* write new mask */
-
-		/* program IO APIC for type 3 INT on INT0 */
-		if (ext_int_setup(0, 0) < 0)
-			panic("8254 redirect impossible!");
-		x = 0;				/* 8259 is on 0 */
-	}
-
-#endif /** NEW_STRATEGY */
-
 	/* setup the vectors */
 	vec[x] = (u_int)vec8254;
 	Xintr8254 = (u_int)ivectors[x];
@@ -966,9 +936,11 @@ cpu_initclocks()
 	if (isa_apic_pin(8) != 8)
 		panic("APIC RTC != 8");
 #endif /* APIC_IO */
+
 	register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0,
 		      /* XXX */ (inthand2_t *)rtcintr, &stat_imask,
 		      /* unit */ 0);
+
 #ifdef APIC_IO
 	INTREN(APIC_IRQ8);
 #else
diff --git a/sys/amd64/isa/isa.c b/sys/amd64/isa/isa.c
index 4d14fff..55066a5 100644
--- a/sys/amd64/isa/isa.c
+++ b/sys/amd64/isa/isa.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
- *	$Id: isa.c,v 1.99 1997/07/29 05:24:36 msmith Exp $
+ *	$Id: isa.c,v 1.2 1997/08/21 04:51:00 smp Exp smp $
  */
 
 /*
@@ -55,7 +55,6 @@
 #include <machine/md_var.h>
 #ifdef APIC_IO
 #include <machine/smp.h>
-#include <machine/apic.h>
 #endif /* APIC_IO */
 #include <vm/vm.h>
 #include <vm/vm_param.h>