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authorjhb <jhb@FreeBSD.org>2006-11-13 22:23:34 +0000
committerjhb <jhb@FreeBSD.org>2006-11-13 22:23:34 +0000
commitfa70d013974c2fa6347ccc628becfdfcdbddc617 (patch)
tree73f5aafc03e3a710fa43be47c1b42fa68959a2bb /sys/amd64/pci
parentd055bdf0ca2fa4ba26cc9a2bf7648eff24fb1cdd (diff)
downloadFreeBSD-src-fa70d013974c2fa6347ccc628becfdfcdbddc617.zip
FreeBSD-src-fa70d013974c2fa6347ccc628becfdfcdbddc617.tar.gz
MD support for PCI Message Signalled Interrupts on amd64 and i386:
- Add a new apic_alloc_vectors() method to the local APIC support code to allocate N contiguous IDT vectors (aligned on a M >= N boundary). This function is used to allocate IDT vectors for a group of MSI messages. - Add MSI and MSI-X PICs. The PIC code here provides methods to manage edge-triggered MSI messages as x86 interrupt sources. In addition to the PIC methods, msi.c also includes methods to allocate and release MSI and MSI-X messages. For x86, we allow for up to 128 different MSI IRQs starting at IRQ 256 (IRQs 0-15 are reserved for ISA IRQs, 16-254 for APIC PCI IRQs, and IRQ 255 is reserved). - Add pcib_(alloc|release)_msi[x]() methods to the MD x86 PCI bridge drivers to bubble the request up to the nexus driver. - Add pcib_(alloc|release)_msi[x]() methods to the x86 nexus drivers that ask the MSI PIC code to allocate resources and IDT vectors. MFC after: 2 months
Diffstat (limited to 'sys/amd64/pci')
-rw-r--r--sys/amd64/pci/pci_bus.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/amd64/pci/pci_bus.c b/sys/amd64/pci/pci_bus.c
index 716b050..6efde3a 100644
--- a/sys/amd64/pci/pci_bus.c
+++ b/sys/amd64/pci/pci_bus.c
@@ -322,6 +322,10 @@ static device_method_t legacy_pcib_methods[] = {
DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
+ DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
+ DEVMETHOD(pcib_release_msi, pcib_release_msi),
+ DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
+ DEVMETHOD(pcib_release_msix, pcib_release_msix),
{ 0, 0 }
};
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