Back out all the pmap related stuff I've touched over the last few days.

There is some unresolved badness that has been eluding me, particularly
affecting uniprocessor kernels.  Turning off PG_G helped (which is a bad
sign) but didn't solve it entirely.  Userland programs still crashed.

3 files changed, 23 insertions, 13 deletions

diff --git a/sys/amd64/isa/intr_machdep.c b/sys/amd64/isa/intr_machdep.c
index 92bf581..cfc162b 100644
--- a/sys/amd64/isa/intr_machdep.c
+++ b/sys/amd64/isa/intr_machdep.c
@@ -499,6 +499,14 @@ icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
 	}
 	else {
 		vector = TPR_SLOW_INTS + intr;
+#ifdef APIC_INTR_REORDER
+#ifdef APIC_INTR_HIGHPRI_CLOCK
+		/* XXX: Hack (kludge?) for more accurate clock. */
+		if (intr == apic_8254_intr || intr == 8) {
+			vector = TPR_FAST_INTS + intr;
+		}
+#endif
+#endif
 		setidt(vector, slowintr[intr],
 		       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 	}
diff --git a/sys/amd64/isa/intr_machdep.h b/sys/amd64/isa/intr_machdep.h
index 789b02b..1726635 100644
--- a/sys/amd64/isa/intr_machdep.h
+++ b/sys/amd64/isa/intr_machdep.h
@@ -88,7 +88,6 @@
 /* IDT vector base for regular (aka. slow) and fast interrupts */
 #define TPR_SLOW_INTS		0x20
 #define TPR_FAST_INTS		0x60
-/* XXX note that the AST interrupt is at 0x50 */
 
 /* blocking values for local APIC Task Priority Register */
 #define TPR_BLOCK_HWI		0x4f		/* hardware INTs */
@@ -105,23 +104,20 @@
 #endif /** TEST_TEST1 */
 
 /* TLB shootdowns */
-#define XINVLTLB_OFFSET		(ICU_OFFSET + 112)	/* 0x90 */
-#define XINVLPG_OFFSET		(ICU_OFFSET + 113)	/* 0x91 */
-#define XINVLRNG_OFFSET		(ICU_OFFSET + 114)	/* 0x92 */
+#define XINVLTLB_OFFSET		(ICU_OFFSET + 112)
 
 /* inter-cpu clock handling */
-#define XHARDCLOCK_OFFSET	(ICU_OFFSET + 120)	/* 0x98 */
-#define XSTATCLOCK_OFFSET	(ICU_OFFSET + 121)	/* 0x99 */
+#define XHARDCLOCK_OFFSET	(ICU_OFFSET + 113)
+#define XSTATCLOCK_OFFSET	(ICU_OFFSET + 114)
 
 /* inter-CPU rendezvous */
-#define XRENDEZVOUS_OFFSET	(ICU_OFFSET + 122)	/* 0x9A */
+#define XRENDEZVOUS_OFFSET	(ICU_OFFSET + 115)
 
 /* IPI to generate an additional software trap at the target CPU */
-/* XXX in the middle of the interrupt range, overlapping IRQ48 */
-#define XCPUAST_OFFSET		(ICU_OFFSET +  48)	/* 0x50 */
+#define XCPUAST_OFFSET		(ICU_OFFSET +  48)
 
 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
-#define XCPUSTOP_OFFSET		(ICU_OFFSET + 128)	/* 0xA0 */
+#define XCPUSTOP_OFFSET		(ICU_OFFSET + 128)
 
 /*
  * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
@@ -185,9 +181,7 @@ inthand_t
 	IDTVEC(intr28), IDTVEC(intr29), IDTVEC(intr30), IDTVEC(intr31);
 
 inthand_t
-	Xinvltlb,	/* TLB shootdowns - global */
-	Xinvlpg,	/* TLB shootdowns - 1 page */
-	Xinvlrng,	/* TLB shootdowns - page range */
+	Xinvltlb,	/* TLB shootdowns */
 	Xhardclock,	/* Forward hardclock() */
 	Xstatclock,	/* Forward statclock() */
 	Xcpuast,	/* Additional software trap on other cpu */ 
diff --git a/sys/amd64/isa/nmi.c b/sys/amd64/isa/nmi.c
index 92bf581..cfc162b 100644
--- a/sys/amd64/isa/nmi.c
+++ b/sys/amd64/isa/nmi.c
@@ -499,6 +499,14 @@ icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
 	}
 	else {
 		vector = TPR_SLOW_INTS + intr;
+#ifdef APIC_INTR_REORDER
+#ifdef APIC_INTR_HIGHPRI_CLOCK
+		/* XXX: Hack (kludge?) for more accurate clock. */
+		if (intr == apic_8254_intr || intr == 8) {
+			vector = TPR_FAST_INTS + intr;
+		}
+#endif
+#endif
 		setidt(vector, slowintr[intr],
 		       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 	}