Initial PG_NX support (no-execute page bit)

- export the rest of the cpu features (and amd's features).
- turn on EFER_NXE, depending on the NX amd feature bit
- reorg the identcpu stuff a bit in order to stop treating the
  amd features as second class features (since it is now a primary feature
  bit set) and make it easier to export.

3 files changed, 22 insertions, 1 deletions

diff --git a/sys/amd64/include/md_var.h b/sys/amd64/include/md_var.h
index 38c18b6..2f37e30 100644
--- a/sys/amd64/include/md_var.h
+++ b/sys/amd64/include/md_var.h
@@ -42,6 +42,8 @@ extern	u_int	basemem;
 extern	int	busdma_swi_pending;
 extern	u_int	cpu_exthigh;
 extern	u_int	cpu_feature;
+extern	u_int	cpu_feature2;
+extern	u_int	amd_feature;
 extern	u_int	cpu_fxsr;
 extern	u_int	cpu_high;
 extern	u_int	cpu_id;
@@ -63,7 +65,7 @@ void	busdma_swi(void);
 void	cpu_setregs(void);
 void	doreti_iret(void) __asm(__STRING(doreti_iret));
 void	doreti_iret_fault(void) __asm(__STRING(doreti_iret_fault));
-void	enable_sse(void);
+void	initializecpu(void);
 void	fillw(int /*u_short*/ pat, void *base, size_t cnt);
 void	fpstate_drop(struct thread *td);
 int	is_physical_memory(vm_paddr_t addr);
diff --git a/sys/amd64/include/pmap.h b/sys/amd64/include/pmap.h
index 746254d..71cfa88 100644
--- a/sys/amd64/include/pmap.h
+++ b/sys/amd64/include/pmap.h
@@ -62,6 +62,7 @@
 #define	PG_AVAIL1	0x200	/*    /	Available for system	*/
 #define	PG_AVAIL2	0x400	/*   <	programmers use		*/
 #define	PG_AVAIL3	0x800	/*    \				*/
+#define	PG_NX		(1ul<<63) /* No-execute */
 
 
 /* Our various interpretations of the above */
@@ -202,6 +203,8 @@ pte_load_store(pt_entry_t *ptep, pt_entry_t pte)
 
 #define	pde_store(pdep, pde)	pte_store((pdep), (pde))
 
+extern pt_entry_t pg_nx;
+
 #endif /* _KERNEL */
 
 /*
diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h
index 905bbf0..37f2328 100644
--- a/sys/amd64/include/specialreg.h
+++ b/sys/amd64/include/specialreg.h
@@ -112,6 +112,22 @@
 #define	CPUID_B30	0x40000000
 #define	CPUID_PBE	0x80000000
 
+#define CPUID2_SSE3	0x00000001
+#define CPUID2_MON	0x00000008
+#define CPUID2_DS_CPL	0x00000010
+#define CPUID2_EST	0x00000080
+#define CPUID2_TM2	0x00000100
+#define CPUID2_CNTXID	0x00000400
+#define CPUID2_CX16	0x00002000
+
+/*
+ * Important bits in the AMD extended cpuid flags
+ */
+#define AMDID_SYSCALL	0x00000800
+#define AMDID_MP	0x00080000
+#define AMDID_NX	0x00100000
+#define AMDID_LM	0x20000000
+
 /*
  * CPUID instruction 1 ebx info
  */