diff options
author | dyson <dyson@FreeBSD.org> | 1996-11-11 04:20:19 +0000 |
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committer | dyson <dyson@FreeBSD.org> | 1996-11-11 04:20:19 +0000 |
commit | 3b0a2952693ec15704f4dc217c9363c79260c647 (patch) | |
tree | f6f5674c338d8e58e7766e38869385db22fbbb15 /sys/amd64/include/specialreg.h | |
parent | eb4f38517ab6b3334eae830239bce13bc11365d4 (diff) | |
download | FreeBSD-src-3b0a2952693ec15704f4dc217c9363c79260c647.zip FreeBSD-src-3b0a2952693ec15704f4dc217c9363c79260c647.tar.gz |
Support the PG_G flag on Pentium-Pro processors. This pretty
much eliminates the unnecessary unmapping of the kernel during
context switches and during invtlb...
Diffstat (limited to 'sys/amd64/include/specialreg.h')
-rw-r--r-- | sys/amd64/include/specialreg.h | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index 9c62438..25e5e63 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 - * $Id: specialreg.h,v 1.8 1996/01/30 22:55:06 mpp Exp $ + * $Id: specialreg.h,v 1.9 1996/06/03 19:37:38 sos Exp $ */ #ifndef _MACHINE_SPECIALREG_H_ @@ -61,6 +61,39 @@ #define CR0_CD 0x40000000 /* Cache Disable */ /* + * Bits in PPro special registers + */ +#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ +#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ +#define CR4_TSD 0x00000004 /* Time stamp disable */ +#define CR4_DE 0x00000008 /* Debugging extensions */ +#define CR4_PSE 0x00000010 /* Page size extensions */ +#define CR4_PAE 0x00000020 /* Physical address extension */ +#define CR4_MCE 0x00000040 /* Machine check enable */ +#define CR4_PGE 0x00000080 /* Page global enable */ +#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ + +/* + * CPUID instruction features register + */ +#define CPUID_FPU 0x0001 +#define CPUID_VME 0x0002 +#define CPUID_DE 0x0004 +#define CPUID_PSE 0x0008 +#define CPUID_TSC 0x0010 +#define CPUID_MSR 0x0020 +#define CPUID_PAE 0x0040 +#define CPUID_MCE 0x0080 +#define CPUID_CX8 0x0100 +#define CPUID_APIC 0x0200 +#define CPUID_B10 0x0400 +#define CPUID_B11 0x0800 +#define CPUID_MTRR 0x1000 +#define CPUID_PGE 0x2000 +#define CPUID_MCA 0x4000 +#define CPUID_CMOV 0x8000 + +/* * Cyrix 486 DLC special registers, accessible as IO ports. */ #define CCR0 0xc0 /* configuration control register 0 */ |