First pass at removing Alpha kernel support.

31 files changed, 0 insertions, 6351 deletions

diff --git a/sys/alpha/pci/alphapci_if.m b/sys/alpha/pci/alphapci_if.m
deleted file mode 100644
index 32b0b5d..0000000
--- a/sys/alpha/pci/alphapci_if.m
+++ /dev/null
@@ -1,59 +0,0 @@
-#-
-# Copyright (c) 2000 Doug Rabson
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in the
-#    documentation and/or other materials provided with the distribution.
-#
-# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-# SUCH DAMAGE.
-#
-# $FreeBSD$
-#
-
-#include <sys/bus.h>
-#include <alpha/pci/pcibus.h>
-
-INTERFACE alphapci;
-
-CODE {
-	static void *null_cvt(device_t dev, vm_offset_t ba)
-	{
-		return 0;
-	}
-};
-
-METHOD void * cvt_dense {
-	device_t	dev;
-	vm_offset_t	ba;
-} DEFAULT null_cvt;
-
-METHOD void * cvt_bwx {
-	device_t	dev;
-	vm_offset_t	ba;
-} DEFAULT null_cvt;
-
-METHOD struct alpha_busspace * get_bustag {
-	device_t	dev;
-	int		type;
-} DEFAULT pci_get_bustag;
-
-METHOD struct rman * get_rman {
-	device_t	dev;
-	int		type;
-} DEFAULT pci_get_rman;
diff --git a/sys/alpha/pci/apecs.c b/sys/alpha/pci/apecs.c
deleted file mode 100644
index a2bbe53..0000000
--- a/sys/alpha/pci/apecs.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- */
-/*-
- * Copyright (c) 1995, 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- * 
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- * 
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-/*-
- * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University 
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/malloc.h>
-#include <sys/module.h>
-#include <sys/mutex.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/proc.h>
-#include <sys/rman.h>
-#include <sys/interrupt.h>
-
-#include <alpha/pci/apecsreg.h>
-#include <alpha/pci/apecsvar.h>
-#include <alpha/isa/isavar.h>
-
-#include <machine/cpuconf.h>
-#include <machine/intr.h>
-#include <machine/intrcnt.h>
-#include <machine/md_var.h>
-#include <machine/resource.h>
-#include <machine/rpb.h>
-#include <machine/sgmap.h>
-#include <machine/swiz.h>
-
-#include <vm/vm.h>
-#include <vm/vm_page.h>
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	apecs_devclass;
-static device_t		apecs0;		/* XXX only one for now */
-
-struct apecs_softc {
-	vm_offset_t	dmem_base;	/* dense memory */
-	vm_offset_t	smem_base;	/* sparse memory */
-	vm_offset_t	io_base;	/* dense i/o */
-	vm_offset_t	cfg0_base;	/* dense pci0 config */
-	vm_offset_t	cfg1_base;	/* dense pci1 config */
-};
-
-#define APECS_SOFTC(dev)	(struct apecs_softc*) device_get_softc(dev)
-
-static alpha_chipset_read_hae_t	apecs_read_hae;
-static alpha_chipset_write_hae_t apecs_write_hae;
-
-static alpha_chipset_t apecs_swiz_chipset = {
-	apecs_read_hae,
-	apecs_write_hae,
-};
-
-/*
- * Memory functions.
- * 
- * XXX linux does 32-bit reads/writes via dense space.  This doesn't
- *     appear to work for devices behind a ppb.  I'm using sparse
- *     accesses & they appear to work just fine everywhere.
- */
-
-static u_int32_t	apecs_hae_mem;
-
-#define REG1 (1UL << 24)
-static u_int32_t
-apecs_set_hae_mem(void *arg, u_int32_t pa)
-{
-	int s; 
-	u_int32_t msb;
-	if (pa >= REG1){
-		msb = pa & 0xf8000000;
-		pa -= msb;
-		s = splhigh();
-                if (msb != apecs_hae_mem) {
-			apecs_hae_mem = msb;
-			REGVAL(EPIC_HAXR1) = apecs_hae_mem;
-			alpha_mb();
-			apecs_hae_mem = REGVAL(EPIC_HAXR1);
-		}
-		splx(s);
-	}
-	return pa;
-}
-
-static u_int64_t
-apecs_read_hae(void)
-{
-	return apecs_hae_mem & 0xf8000000;
-}
-
-static void
-apecs_write_hae(u_int64_t hae)
-{
-	u_int32_t pa = hae;
-	apecs_set_hae_mem(0, pa);
-}
-
-static int apecs_probe(device_t dev);
-static int apecs_attach(device_t dev);
-static int apecs_setup_intr(device_t dev, device_t child,
-			    struct resource *irq, int flags,
-			    driver_intr_t *intr, void *arg, void **cookiep);
-static int apecs_teardown_intr(device_t dev, device_t child,
-			     struct resource *irq, void *cookie);
-
-static device_method_t apecs_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		apecs_probe),
-	DEVMETHOD(device_attach,	apecs_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_setup_intr,	apecs_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	apecs_teardown_intr),
-
-	{ 0, 0 }
-};
-
-static driver_t apecs_driver = {
-	"apecs",
-	apecs_methods,
-	sizeof(struct apecs_softc),
-};
-
-#define APECS_SGMAP_BASE		(8*1024*1024)
-#define APECS_SGMAP_SIZE		(8*1024*1024)
-
-static void
-apecs_sgmap_invalidate(void)
-{
-	alpha_mb();
-	REGVAL(EPIC_TBIA) = 0;
-	alpha_mb();
-}
-
-static void
-apecs_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
-{
-	u_int64_t *sgtable = arg;
-	int index = alpha_btop(ba - APECS_SGMAP_BASE);
-
-	if (pa) {
-		if (pa > (1L<<32))
-			panic("apecs_sgmap_map: can't map address 0x%lx", pa);
-		sgtable[index] = ((pa >> 13) << 1) | 1;
-	} else {
-		sgtable[index] = 0;
-	}
-	alpha_mb();
-	apecs_sgmap_invalidate();
-}
-
-static void
-apecs_init_sgmap(void)
-{
-	void *sgtable;
-
-	/*
-	 * First setup Window 0 to map 8Mb to 16Mb with an
-	 * sgmap. Allocate the map aligned to a 32 boundary.
-	 */
-	REGVAL(EPIC_PCI_BASE_1) = APECS_SGMAP_BASE |
-		EPIC_PCI_BASE_SGEN | EPIC_PCI_BASE_WENB;
-	alpha_mb();
-
-	REGVAL(EPIC_PCI_MASK_1) = EPIC_PCI_MASK_8M;
-	alpha_mb();
-
-	sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
-			       0, (1L<<34),
-			       32*1024, (1L<<34));
-	if (!sgtable)
-		panic("apecs_init_sgmap: can't allocate page table");
-	REGVAL(EPIC_TBASE_1) =
-		(pmap_kextract((vm_offset_t) sgtable) >> EPIC_TBASE_SHIFT);
-
-	chipset.sgmap = sgmap_map_create(APECS_SGMAP_BASE,
-					 APECS_SGMAP_BASE + APECS_SGMAP_SIZE,
-					 apecs_sgmap_map, sgtable);
-	chipset.pci_sgmap = NULL;
-	chipset.dmsize = 1UL * 1024UL * 1024UL * 1024UL;
-	chipset.dmoffset = 1UL * 1024UL * 1024UL * 1024UL;
-}
-
-void
-apecs_init()
-{
-	static int initted = 0;
-	static struct swiz_space io_space, mem_space;
-
-	if (initted) return;
-	initted = 1;
-
-	swiz_init_space(&io_space, KV(APECS_PCI_SIO));
-	swiz_init_space_hae(&mem_space, KV(APECS_PCI_SPARSE),
-			    apecs_set_hae_mem, 0);
-
-	busspace_isa_io = (struct alpha_busspace *) &io_space;
-	busspace_isa_mem = (struct alpha_busspace *) &mem_space;
-
-	chipset = apecs_swiz_chipset;
-
-	if (platform.pci_intr_init)
-		platform.pci_intr_init();
-
-}
-
-static int
-apecs_probe(device_t dev)
-{
-	int memwidth;
-	if (apecs0)
-		return ENXIO;
-	apecs0 = dev;
-	memwidth = (REGVAL(COMANCHE_GCR) & COMANCHE_GCR_WIDEMEM) != 0 ? 128 : 64;
-	if(memwidth == 64){
-		device_set_desc(dev, "DECchip 21071 Core Logic chipset");
-	} else {
-		device_set_desc(dev, "DECchip 21072 Core Logic chipset");
-	}
-	apecs_hae_mem = REGVAL(EPIC_HAXR1);
-
-	isa_init_intr();
-	apecs_init_sgmap();
-
-	device_add_child(dev, "pcib", 0);
-
-	return 0;
-}
-
-static int
-apecs_attach(device_t dev)
-{
-	struct apecs_softc* sc = APECS_SOFTC(dev);
-	apecs_init();
-
-	sc->dmem_base = APECS_PCI_DENSE;
-	sc->smem_base = APECS_PCI_SPARSE;
-	sc->io_base = APECS_PCI_SIO;
-	sc->cfg0_base = KV(APECS_PCI_CONF);
-	sc->cfg1_base = 0;
-
-	set_iointr(alpha_dispatch_intr);
-
-	snprintf(chipset_type, sizeof(chipset_type), "apecs");
-	chipset_bwx = 0;
-	chipset_ports = APECS_PCI_SIO;
-	chipset_memory = APECS_PCI_SPARSE;
-	chipset_dense = APECS_PCI_DENSE;
-	chipset_hae_mask = EPIC_HAXR1_EADDR;
-
-	bus_generic_attach(dev);
-	return 0;
-}
-
-static void
-apecs_disable_intr(uintptr_t vector)
-{
-	int irq;
-
-	irq = (vector - 0x900) >> 4;
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_disable(irq);
-	mtx_unlock_spin(&icu_lock);
-}
-
-static void
-apecs_enable_intr(uintptr_t vector)
-{
-	int irq;
-
-	irq = (vector - 0x900) >> 4;
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_enable(irq);
-	mtx_unlock_spin(&icu_lock);
-}
-
-static int
-apecs_setup_intr(device_t dev, device_t child,
-	       struct resource *irq, int flags,
-	       driver_intr_t *intr, void *arg, void **cookiep)
-{
-	int error, start;
-	
-	start = rman_get_start(irq);
-	/* 
-	 *  the avanti routes interrupts through the isa interrupt
-	 *  controller, so we need to special case it 
-	 */
-	if(hwrpb->rpb_type == ST_DEC_2100_A50)
-		return isa_setup_intr(dev, child, irq, flags,
-				      intr, arg, cookiep);
-
-	error = rman_activate_resource(irq);
-	if (error)
-		return error;
-
-	error = alpha_setup_intr(device_get_nameunit(child ? child : dev),
-			0x900 + (start << 4), intr, arg, flags, cookiep,
-			&intrcnt[INTRCNT_EB64PLUS_IRQ + start],
-			apecs_disable_intr, apecs_enable_intr);
-	if (error)
-		return error;
-
-	/* Enable PCI interrupt */
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_enable(start);
-	mtx_unlock_spin(&icu_lock);
-
-	device_printf(child, "interrupting at APECS irq %d\n", start);
-		      
-
-
-	return 0;
-}
-
-static int
-apecs_teardown_intr(device_t dev, device_t child,
-		  struct resource *irq, void *cookie)
-{
-	/* 
-	 *  the avanti routes interrupts through the isa interrupt
-	 *  controller, so we need to special case it 
-	 */
-	if(hwrpb->rpb_type == ST_DEC_2100_A50)
-		return isa_teardown_intr(dev, child, irq, cookie);
-
-	alpha_teardown_intr(cookie);
-	return rman_deactivate_resource(irq);
-}
-
-DRIVER_MODULE(apecs, root, apecs_driver, apecs_devclass, 0, 0);
-
diff --git a/sys/alpha/pci/apecs_pci.c b/sys/alpha/pci/apecs_pci.c
deleted file mode 100644
index 40af5cc..0000000
--- a/sys/alpha/pci/apecs_pci.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPEAPECSL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-#include <machine/cpuconf.h>
-#include <machine/swiz.h>
-#include <machine/md_var.h>
-#include <machine/rpb.h>
-#include <machine/resource.h>
-
-#include <alpha/pci/apecsreg.h>
-#include <alpha/pci/apecsvar.h>
-#include <alpha/pci/pcibus.h>
-#include <alpha/isa/isavar.h>
-
-#include "alphapci_if.h"
-#include "pcib_if.h"
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	pcib_devclass;
-
-static int
-apecs_pcib_probe(device_t dev)
-{
-	device_set_desc(dev, "2107x PCI host bus adapter");
-
-	pci_init_resources();
-	device_add_child(dev, "pci", 0);
-
-	return 0;
-}
-
-static int
-apecs_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
-{
-	if (which == PCIB_IVAR_BUS) {
-		*result = 0;
-		return 0;
-	}
-	return ENOENT;
-}
-
-static struct resource *
-apecs_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
-			  u_long start, u_long end, u_long count, u_int flags)
-{
-	struct resource *rv = NULL;
-
-	if ((hwrpb->rpb_type == ST_DEC_2100_A50) &&
-	    (type == SYS_RES_IRQ))
-		rv = isa_alloc_intr(bus, child, start);
-	else
-		rv = alpha_pci_alloc_resource(bus, child, type, rid,
-		    start, end, count, flags);
-	if (rv != NULL)
-		rman_set_rid(rv, *rid);
-	return (rv);
-}
-
-static int
-apecs_pcib_release_resource(device_t bus, device_t child, int type, int rid,
-			    struct resource *r)
-{
-	if ((hwrpb->rpb_type == ST_DEC_2100_A50) &&
-	    (type == SYS_RES_IRQ))
-		return isa_release_intr(bus, child, r);
-	else
-		return pci_release_resource(bus, child, type, rid, r);
-}
-
-static void *
-apecs_pcib_cvt_dense(device_t dev, vm_offset_t addr)
-{
-	addr &= 0xffffffffUL;
-	return (void *) KV(addr | APECS_PCI_DENSE);
-}
-
-static int
-apecs_pcib_maxslots(device_t dev)
-{
-	return 31;
-}
-
-#define APECS_SWIZ_CFGOFF(b, s, f, r) \
-	(((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
-
-#define APECS_TYPE1_SETUP(b,s,old_haxr2) if((b)) {	\
-        do {						\
-		(s) = splhigh();			\
-		(old_haxr2) = REGVAL(EPIC_HAXR2);	\
-		alpha_mb();				\
-		REGVAL(EPIC_HAXR2) = (old_haxr2) | 0x1;	\
-		alpha_mb();				\
-        } while(0);					\
-}
-
-#define APECS_TYPE1_TEARDOWN(b,s,old_haxr2) if((b)) {	\
-        do {						\
-		alpha_mb();				\
-		REGVAL(EPIC_HAXR2) = (old_haxr2);	\
-		alpha_mb();				\
-		splx((s));				\
-        } while(0);					\
-}
-
-#define SWIZ_CFGREAD(b, s, f, r, width, type) do {			\
-	type val = ~0;							\
-	int ipl = 0;							\
-	u_int32_t old_haxr2 = 0;					\
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);		\
-	vm_offset_t kv =						\
-		SPARSE_##width##_ADDRESS(KV(APECS_PCI_CONF), off);	\
-	alpha_mb();							\
-	APECS_TYPE1_SETUP(b,ipl,old_haxr2);				\
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			\
-		val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv));	\
-	}								\
-        APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2);				\
-	return val;							\
-} while (0)
-
-#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) do {		\
-	int ipl = 0;							\
-	u_int32_t old_haxr2 = 0;					\
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);		\
-	vm_offset_t kv =						\
-		SPARSE_##width##_ADDRESS(KV(APECS_PCI_CONF), off);	\
-	alpha_mb();							\
-	APECS_TYPE1_SETUP(b,ipl,old_haxr2);				\
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			\
-                SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data));	\
-		alpha_wmb();						\
-	}								\
-        APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2);				\
-	return;								\
-} while (0)
-
-u_int32_t
-apecs_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
-		       u_int reg, int width)
-{
-	pcicfgregs cfg;
-
-	if ((reg == PCIR_INTLINE) && (width == 1) && 
-	     (platform.pci_intr_map != NULL)) {
-		cfg.bus = b;
-		cfg.slot = s;
-		cfg.func = f;
-		cfg.intline = 255;
-		cfg.intpin =
-		    apecs_pcib_read_config(dev, b, s, f, PCIR_INTPIN, 1);
-		platform.pci_intr_map((void *)&cfg);
-		if (cfg.intline != 255)
-			return cfg.intline;
-	}
-
-	switch (width) {
-	case 1:
-		SWIZ_CFGREAD(b, s, f, reg, BYTE, u_int8_t);
-		break;
-	case 2:
-		SWIZ_CFGREAD(b, s, f, reg, WORD, u_int16_t);
-		break;
-	case 4:
-		SWIZ_CFGREAD(b, s, f, reg, LONG, u_int32_t);
-	}
-	return ~0;
-}
-
-static void
-apecs_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
-			u_int reg, u_int32_t val, int width)
-{
-	switch (width) {
-	case 1:
-		SWIZ_CFGWRITE(b, s, f, reg, val, BYTE, u_int8_t);
-		break;
-	case 2:
-		SWIZ_CFGWRITE(b, s, f, reg, val, WORD, u_int16_t);
-		break;
-	case 4:
-		SWIZ_CFGWRITE(b, s, f, reg, val, LONG, u_int32_t);
-	}
-}
-
-static device_method_t apecs_pcib_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		apecs_pcib_probe),
-	DEVMETHOD(device_attach,	bus_generic_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_read_ivar,	apecs_pcib_read_ivar),
-	DEVMETHOD(bus_alloc_resource,	apecs_pcib_alloc_resource),
-	DEVMETHOD(bus_release_resource,	apecs_pcib_release_resource),
-	DEVMETHOD(bus_activate_resource, pci_activate_resource),
-	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
-	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
-
-	/* alphapci interface */
-	DEVMETHOD(alphapci_cvt_dense,	apecs_pcib_cvt_dense),
-
-	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,	apecs_pcib_maxslots),
-	DEVMETHOD(pcib_read_config,	apecs_pcib_read_config),
-	DEVMETHOD(pcib_write_config,	apecs_pcib_write_config),
-	DEVMETHOD(pcib_route_interrupt,	alpha_pci_route_interrupt),
-
-	{ 0, 0 }
-};
-
-static driver_t apecs_pcib_driver = {
-	"pcib",
-	apecs_pcib_methods,
-	1,
-};
-
-DRIVER_MODULE(pcib, apecs, apecs_pcib_driver, pcib_devclass, 0, 0);
diff --git a/sys/alpha/pci/apecsreg.h b/sys/alpha/pci/apecsreg.h
deleted file mode 100644
index a9e180b..0000000
--- a/sys/alpha/pci/apecsreg.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/* $FreeBSD$ */
-/* $NetBSD: apecsreg.h,v 1.7 1997/06/06 23:54:24 thorpej Exp $ */
-
-/*-
- * Copyright (c) 1995 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- * 
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- * 
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-/*
- * APECS Chipset registers and constants.
- *
- * Taken from ``DECchip 21071 and DECchip 21072 Core Logic Chipsets Data
- * Sheet'' (DEC order number EC-QAEMA-TE), pages 4-1 - 4-27, 10-21 - 10-38.
- */
-
-#define	REGVAL(r)	(*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
-
-/*
- * Base addresses
- */
-#define	COMANCHE_BASE	 0x180000000L			/* 21071-CA Regs */
-#define	EPIC_BASE	 0x1a0000000L			/* 21071-DA Regs */
-#define	APECS_PCI_IACK	 0x1b0000000L			/* PCI Int. Ack. */
-#define	APECS_PCI_SIO	 0x1c0000000L			/* PCI Sp. I/O Space */
-#define	APECS_PCI_CONF	 0x1e0000000L			/* PCI Conf. Space */
-#define	APECS_PCI_SPARSE 0x200000000L			/* PCI Sparse Space */
-#define	APECS_PCI_DENSE	 0x300000000L			/* PCI Dense Space */
-
-
-/*
- * 21071-CA Registers
- */
-
-/*
- * 21071-CA General Registers
- */
-#define	COMANCHE_GCR	(COMANCHE_BASE + 0x0000)	/* General Control */
-#define		COMANCHE_GCR_RSVD	0xc009
-#define		COMANCHE_GCR_SYSARB	0x0006
-#define		COMANCHE_GCR_WIDEMEM	0x0010
-#define		COMANCHE_GCR_BC_EN	0x0020
-#define		COMANCHE_GCR_BC_NOALLOC	0x0040
-#define		COMANCHE_GCR_BC_LONGWR	0x0080
-#define		COMANCHE_GCR_BC_IGNTAG	0x0100
-#define		COMANCHE_GCR_BC_FRCTAG	0x0200
-#define		COMANCHE_GCR_BC_FRCD	0x0400
-#define		COMANCHE_GCR_BC_FRCV	0x0800
-#define		COMANCHE_GCR_BC_FRCP	0x1000
-#define		COMANCHE_GCR_BC_BADAP	0x2000
-
-#define	COMANCHE_RSVD	(COMANCHE_BASE + 0x0020)	/* Reserved */
-
-#define	COMANCHE_ED	(COMANCHE_BASE + 0x0040)	/* Err & Diag Status */
-#define		COMANCHE_ED_LOSTERR	0x0001
-#define		COMANCHE_ED_BC_TAPERR	0x0002
-#define		COMANCHE_ED_BC_TCPERR	0x0004
-#define		COMANCHE_ED_NXMERR	0x0008
-#define		COMANCHE_ED_DMACAUSE	0x0010
-#define		COMANCHE_ED_VICCAUSE	0x0020
-#define		COMANCHE_ED_CREQCAUSE	0x01c0
-#define		COMANCHE_ED_RSVD	0x1e00
-#define		COMANCHE_ED_PASS2	0x2000
-#define		COMANCHE_ED_IDXLLOCK	0x4000
-#define		COMANCHE_ED_WRPEND	0x8000
-
-#define	COMANCHE_TAGENB	(COMANCHE_BASE + 0x0060)	/* Tag Enable */
-#define		COMANCHE_TAGENB_RSVD	0x0001
-
-#define		COMANCHE_TAGENB_C_4G	0x0000
-#define		COMANCHE_TAGENB_C_2G	0x8000
-#define		COMANCHE_TAGENB_C_1G	0xc000
-#define		COMANCHE_TAGENB_C_512M	0xe000
-#define		COMANCHE_TAGENB_C_256M	0xf000
-#define		COMANCHE_TAGENB_C_128M	0xf800
-#define		COMANCHE_TAGENB_C_64M	0xfc00
-#define		COMANCHE_TAGENB_C_32M	0xfe00
-#define		COMANCHE_TAGENB_C_16M	0xff00
-#define		COMANCHE_TAGENB_C_8M	0xff80
-#define		COMANCHE_TAGENB_C_4M	0xffc0
-#define		COMANCHE_TAGENB_C_2M	0xffe0
-#define		COMANCHE_TAGENB_C_1M	0xfff0
-#define		COMANCHE_TAGENB_C_512K	0xfff8
-#define		COMANCHE_TAGENB_C_256K	0xfffc
-#define		COMANCHE_TAGENB_C_128K	0xfffe
-
-#define		COMANCHE_TAGENB_M_4G	0xffff
-#define		COMANCHE_TAGENB_M_2G	0x7fff
-#define		COMANCHE_TAGENB_M_1G	0x3fff
-#define		COMANCHE_TAGENB_M_512M	0x1fff
-#define		COMANCHE_TAGENB_M_256M	0x0fff
-#define		COMANCHE_TAGENB_M_128M	0x07ff
-#define		COMANCHE_TAGENB_M_64M	0x03ff
-#define		COMANCHE_TAGENB_M_32M	0x01ff
-#define		COMANCHE_TAGENB_M_16M	0x00ff
-#define		COMANCHE_TAGENB_M_8M	0x007f
-#define		COMANCHE_TAGENB_M_4M	0x003f
-#define		COMANCHE_TAGENB_M_2M	0x001f
-#define		COMANCHE_TAGENB_M_1M	0x000e
-#define		COMANCHE_TAGENB_M_512K	0x0006
-#define		COMANCHE_TAGENB_M_256K	0x0002
-#define		COMANCHE_TAGENB_M_128K	0x0000
-
-#define	COMANCHE_ERR_LO	(COMANCHE_BASE + 0x0080)	/* Error Low Address */
-
-#define	COMANCHE_ERR_HI	(COMANCHE_BASE + 0x00a0)	/* Error High Address */
-#define		COMANCHE_ERR_HI_RSVD	0xe000
-
-#define	COMANCHE_LCK_LO	(COMANCHE_BASE + 0x00c0)	/* LDx_L Low Address */
-
-#define	COMANCHE_LCK_HI	(COMANCHE_BASE + 0x00e0)	/* LDx_L High Address */
-#define		COMANCHE_LOCK_HI_RSVD	0xe000
-
-/*
- * 21071-CA Memory Registers
- */
-#define	COMANCHE_GTIM	(COMANCHE_BASE + 0x0200)	 /* Global Timing */
-#define		COMANCHE_LOCK_HI_RSVD	0xe000
-
-#define	COMANCHE_RTIM	(COMANCHE_BASE + 0x0220)	 /* Refresh Timing */
-
-#define	COMANCHE_VFP	(COMANCHE_BASE + 0x0240)	 /* Video Frame Ptr. */
-#define		COMANCHE_VFP_COL	0x001f
-#define		COMANCHE_VFP_ROW	0x3fe0
-#define		COMANCHE_VFP_SUBBANK	0x4000
-#define		COMANCHE_VFP_RSVD	0x8000
-
-#define	COMANCHE_PD_LO	(COMANCHE_BASE + 0x0260)	/* Pres Detect Low */
-
-#define	COMANCHE_PD_HI	(COMANCHE_BASE + 0x0280)	/* Pres Detect High */
-
-/*
- * 21071-CA Memory banks' Base Address Register format
- */
-#define	COMANCHE_B0_BAR	(COMANCHE_BASE + 0x0800)	/* Bank 0 BA */
-#define	COMANCHE_B1_BAR	(COMANCHE_BASE + 0x0820)	/* Bank 1 BA */
-#define	COMANCHE_B2_BAR	(COMANCHE_BASE + 0x0840)	/* Bank 2 BA */
-#define	COMANCHE_B3_BAR	(COMANCHE_BASE + 0x0860)	/* Bank 3 BA */
-#define	COMANCHE_B4_BAR	(COMANCHE_BASE + 0x0880)	/* Bank 4 BA */
-#define	COMANCHE_B5_BAR	(COMANCHE_BASE + 0x08a0)	/* Bank 5 BA */
-#define	COMANCHE_B6_BAR	(COMANCHE_BASE + 0x08c0)	/* Bank 6 BA */
-#define	COMANCHE_B7_BAR	(COMANCHE_BASE + 0x08e0)	/* Bank 7 BA */
-#define	COMANCHE_B8_BAR	(COMANCHE_BASE + 0x0900)	/* Bank 8 BA */
-#define		COMANCHE_BAR_RSVD	0x001f
-
-/*
- * 21071-CA Memory banks' Configuration Register format
- */
-#define	COMANCHE_B0_CR	(COMANCHE_BASE + 0x0a00)	/* Bank 0 Config */
-#define	COMANCHE_B1_CR	(COMANCHE_BASE + 0x0a20)	/* Bank 1 Config */
-#define	COMANCHE_B2_CR	(COMANCHE_BASE + 0x0a40)	/* Bank 2 Config */
-#define	COMANCHE_B3_CR	(COMANCHE_BASE + 0x0a60)	/* Bank 3 Config */
-#define	COMANCHE_B4_CR	(COMANCHE_BASE + 0x0a80)	/* Bank 4 Config */
-#define	COMANCHE_B5_CR	(COMANCHE_BASE + 0x0aa0)	/* Bank 5 Config */
-#define	COMANCHE_B6_CR	(COMANCHE_BASE + 0x0ac0)	/* Bank 6 Config */
-#define	COMANCHE_B7_CR	(COMANCHE_BASE + 0x0ae0)	/* Bank 7 Config */
-#define	COMANCHE_B8_CR	(COMANCHE_BASE + 0x0b00)	/* Bank 8 Config */
-#define		COMANCHE_CR_VALID	0x0001
-#define		COMANCHE_CR_SIZE	0x001e
-#define		COMANCHE_CR_SUBENA	0x0020
-#define		COMANCHE_CR_COLSEL	0x01c0
-#define		COMANCHE_CR_S0_RSVD	0xfe00
-#define		COMANCHE_CR_S8_CHECK	0x0200
-#define		COMANCHE_CR_S8_RSVD	0xfc00
-
-/*
- * 21071-CA Memory banks' Timing Register A format
- */
-#define	COMANCHE_B0_TRA	(COMANCHE_BASE + 0x0c00)	/* Bank 0 Timing A */
-#define	COMANCHE_B1_TRA	(COMANCHE_BASE + 0x0c20)	/* Bank 1 Timing A */
-#define	COMANCHE_B2_TRA	(COMANCHE_BASE + 0x0c40)	/* Bank 2 Timing A */
-#define	COMANCHE_B3_TRA	(COMANCHE_BASE + 0x0c60)	/* Bank 3 Timing A */
-#define	COMANCHE_B4_TRA	(COMANCHE_BASE + 0x0c80)	/* Bank 4 Timing A */
-#define	COMANCHE_B5_TRA	(COMANCHE_BASE + 0x0ca0)	/* Bank 5 Timing A */
-#define	COMANCHE_B6_TRA	(COMANCHE_BASE + 0x0cc0)	/* Bank 6 Timing A */
-#define	COMANCHE_B7_TRA	(COMANCHE_BASE + 0x0ce0)	/* Bank 7 Timing A */
-#define	COMANCHE_B8_TRA	(COMANCHE_BASE + 0x0d00)	/* Bank 8 Timing A */
-#define		COMANCHE_TRA_ROWSETUP	0x0003
-#define		COMANCHE_TRA_ROWHOLD	0x000c
-#define		COMANCHE_TRA_COLSETUP	0x0070
-#define		COMANCHE_TRA_COLHOLD	0x0180
-#define		COMANCHE_TRA_RDLYROW	0x0e00
-#define		COMANCHE_TRA_RDLYCOL	0x7000
-#define		COMANCHE_TRA_RSVD	0x8000
-
-/*
- * 21071-CA Memory banks' Timing Register B format
- */
-#define	COMANCHE_B0_TRB	(COMANCHE_BASE + 0x0e00)	/* Bank 0 Timing B */
-#define	COMANCHE_B1_TRB	(COMANCHE_BASE + 0x0e20)	/* Bank 1 Timing B */
-#define	COMANCHE_B2_TRB	(COMANCHE_BASE + 0x0e40)	/* Bank 2 Timing B */
-#define	COMANCHE_B3_TRB	(COMANCHE_BASE + 0x0e60)	/* Bank 3 Timing B */
-#define	COMANCHE_B4_TRB	(COMANCHE_BASE + 0x0e80)	/* Bank 4 Timing B */
-#define	COMANCHE_B5_TRB	(COMANCHE_BASE + 0x0ea0)	/* Bank 5 Timing B */
-#define	COMANCHE_B6_TRB	(COMANCHE_BASE + 0x0ec0)	/* Bank 6 Timing B */
-#define	COMANCHE_B7_TRB	(COMANCHE_BASE + 0x0ee0)	/* Bank 7 Timing B */
-#define	COMANCHE_B8_TRB	(COMANCHE_BASE + 0x0f00)	/* Bank 8 Timing B */
-#define		COMANCHE_TRB_RTCAS	0x0007
-#define		COMANCHE_TRB_WTCAS	0x0038
-#define		COMANCHE_TRB_TCP	0x00c0
-#define		COMANCHE_TRB_WHOLD0ROW	0x0700
-#define		COMANCHE_TRB_WHOLD0COL	0x3800
-#define		COMANCHE_TRB_RSVD	0xc000
-
-
-/*
- * 21071-DA Registers
- */
-#define	EPIC_DCSR	(EPIC_BASE + 0x0000)		/* Diagnostic CSR */
-#define		EPIC_DCSR_TENB		0x00000001
-#define		EPIC_DCSR_RSVD		0x7fc00082
-#define		EPIC_DCSR_PENB		0x00000004
-#define		EPIC_DCSR_DCEI		0x00000008
-#define		EPIC_DCSR_DPEC		0x00000010
-#define		EPIC_DCSR_IORT		0x00000020
-#define		EPIC_DCSR_LOST		0x00000040
-#define		EPIC_DCSR_DDPE		0x00000100
-#define		EPIC_DCSR_IOPE		0x00000200
-#define		EPIC_DCSR_TABT		0x00000400
-#define		EPIC_DCSR_NDEV		0x00000800
-#define		EPIC_DCSR_CMRD		0x00001000
-#define		EPIC_DCSR_UMRD		0x00002000
-#define		EPIC_DCSR_IPTL		0x00004000
-#define		EPIC_DCSR_MERR		0x00008000
-#define		EPIC_DCSR_DBYP		0x00030000
-#define		EPIC_DCSR_PCMD		0x003c0000
-#define		EPIC_DCSR_PASS2		0x80000000
-
-#define	EPIC_PEAR	(EPIC_BASE + 0x0020)		/* PCI Err Addr. */
-
-#define	EPIC_SEAR	(EPIC_BASE + 0x0040)		/* sysBus Err Addr. */
-#define		EPIC_SEAR_RSVD		0x0000000f
-#define		EPIC_SEAR_SYS_ERR	0xfffffff0
-
-#define	EPIC_DUMMY_1	(EPIC_BASE + 0x0060)		/* Dummy 1 */
-#define	EPIC_DUMMY_2	(EPIC_BASE + 0x0080)		/* Dummy 2 */
-#define	EPIC_DUMMY_3	(EPIC_BASE + 0x00a0)		/* Dummy 3 */
-
-#define	EPIC_TBASE_1	(EPIC_BASE + 0x00c0)		/* Trans. Base 1 */
-#define	EPIC_TBASE_2	(EPIC_BASE + 0x00e0)		/* Trans. Base 2 */
-#define		EPIC_TBASE_RSVD		0x000001ff
-#define		EPIC_TBASE_T_BASE	0xfffffe00
-#define		EPIC_TBASE_SHIFT	1
-
-#define	EPIC_PCI_BASE_1	(EPIC_BASE + 0x0100)		/* PCI Base 1 */
-#define	EPIC_PCI_BASE_2	(EPIC_BASE + 0x0120)		/* PCI Base 2 */
-#define		EPIC_PCI_BASE_RSVD	0x0003ffff
-#define		EPIC_PCI_BASE_SGEN	0x00040000
-#define		EPIC_PCI_BASE_WENB	0x00080000
-#define		EPIC_PCI_BASE_PCI_BASE	0xfff00000
-
-#define	EPIC_PCI_MASK_1	(EPIC_BASE + 0x0140)		/* PCI Mask 1 */
-#define	EPIC_PCI_MASK_2	(EPIC_BASE + 0x0160)		/* PCI Mask 2 */
-#define		EPIC_PCI_MASK_RSVD	0x000fffff
-#define		EPIC_PCI_MASK_PCI_MASK	0xfff00000
-#define		EPIC_PCI_MASK_1M	0x00000000
-#define		EPIC_PCI_MASK_2M	0x00100000
-#define		EPIC_PCI_MASK_4M	0x00300000
-#define		EPIC_PCI_MASK_8M	0x00700000
-#define		EPIC_PCI_MASK_16M	0x00f00000
-#define		EPIC_PCI_MASK_32M	0x01f00000
-#define		EPIC_PCI_MASK_64M	0x03f00000
-#define		EPIC_PCI_MASK_128M	0x07f00000
-#define		EPIC_PCI_MASK_256M	0x0ff00000
-#define		EPIC_PCI_MASK_512M	0x1ff00000
-#define		EPIC_PCI_MASK_1G	0x3ff00000
-#define		EPIC_PCI_MASK_2G	0x7ff00000
-#define		EPIC_PCI_MASK_4G	0xfff00000
-
-#define	EPIC_HAXR0	(EPIC_BASE + 0x0180)		/* Host Addr Extn 0 */
-
-#define	EPIC_HAXR1	(EPIC_BASE + 0x01a0)		/* Host Addr Extn 1 */
-#define		EPIC_HAXR1_RSVD		0x07ffffff
-#define		EPIC_HAXR1_EADDR	0xf8000000
-
-#define	EPIC_HAXR2	(EPIC_BASE + 0x01c0)		/* Host Addr Extn 2 */
-#define		EPIC_HAXR2_CONF_TYPE	0x00000003
-#define		EPIC_HAXR2_CONF_TYPO0	0x00000000
-#define		EPIC_HAXR2_CONF_TYPE1	0x00000001
-#define		EPIC_HAXR2_RSVD		0x00fffffc
-#define		EPIC_HAXR2_EADDR	0xff000000
-
-#define	EPIC_PMLT	(EPIC_BASE + 0x01e0)		/* PCI Mstr Lat Tmr */
-#define		EPIC_PMLT_PMLC		0x000000ff
-#define		EPIC_PMLT_RSVD		0xffffff00
-
-#define	EPIC_TLB_TAG_0	(EPIC_BASE + 0x0200)		/* TLB Tag 0 */
-#define	EPIC_TLB_TAG_1	(EPIC_BASE + 0x0220)		/* TLB Tag 1 */
-#define	EPIC_TLB_TAG_2	(EPIC_BASE + 0x0240)		/* TLB Tag 2 */
-#define	EPIC_TLB_TAG_3	(EPIC_BASE + 0x0260)		/* TLB Tag 3 */
-#define	EPIC_TLB_TAG_4	(EPIC_BASE + 0x0280)		/* TLB Tag 4 */
-#define	EPIC_TLB_TAG_5	(EPIC_BASE + 0x02a0)		/* TLB Tag 5 */
-#define	EPIC_TLB_TAG_6	(EPIC_BASE + 0x02c0)		/* TLB Tag 6 */
-#define	EPIC_TLB_TAG_7	(EPIC_BASE + 0x02e0)		/* TLB Tag 7 */
-#define		EPIC_TLB_TAG_RSVD	0x00000fff
-#define		EPIC_TLB_TAG_EVAL	0x00001000
-#define		EPIC_TLB_TAG_PCI_PAGE	0xffffe000
-
-#define	EPIC_TLB_DATA_0	(EPIC_BASE + 0x0300)		/* TLB Data 0 */
-#define	EPIC_TLB_DATA_1	(EPIC_BASE + 0x0320)		/* TLB Data 1 */
-#define	EPIC_TLB_DATA_2	(EPIC_BASE + 0x0340)		/* TLB Data 2 */
-#define	EPIC_TLB_DATA_3	(EPIC_BASE + 0x0360)		/* TLB Data 3 */
-#define	EPIC_TLB_DATA_4	(EPIC_BASE + 0x0380)		/* TLB Data 4 */
-#define	EPIC_TLB_DATA_5	(EPIC_BASE + 0x03a0)		/* TLB Data 5 */
-#define	EPIC_TLB_DATA_6	(EPIC_BASE + 0x03c0)		/* TLB Data 6 */
-#define	EPIC_TLB_DATA_7	(EPIC_BASE + 0x03e0)		/* TLB Data 7 */
-#define		EPIC_TLB_DATA_RSVD	0xffe00001
-#define		EPIC_TLB_DATA_CPU_PAGE	0x001ffffe
-
-#define	EPIC_TBIA	(EPIC_BASE + 0x0400)		/* TLB Invl All */
-
-/*
- * EPIC Scatter-Gather Map Entries
- */
-
-struct sgmapent {
-	u_int64_t val;
-};
-#define	SGMAPENT_EVAL	0x0000000000000001L
-#define	SGMAPENT_PFN	0x00000000001ffffeL
-#define	SGMAPENT_RSVD	0xffffffffffe00000L
-
-#define	SGMAP_MAKEENTRY(pfn)	(SGMAPENT_EVAL | ((pfn) << 1))
diff --git a/sys/alpha/pci/apecsvar.h b/sys/alpha/pci/apecsvar.h
deleted file mode 100644
index 2c6987e..0000000
--- a/sys/alpha/pci/apecsvar.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-struct device;
-
-extern void apecs_init(void);
-u_int32_t apecs_pcib_read_config(struct device *dev, u_int b, u_int s, u_int f,
-				 u_int reg, int width);
diff --git a/sys/alpha/pci/bwx.c b/sys/alpha/pci/bwx.c
deleted file mode 100644
index fd63ebb..0000000
--- a/sys/alpha/pci/bwx.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*-
- * Copyright (c) 2000 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/kobj.h>
-
-#include <machine/bus.h>
-#include <machine/bwx.h>
-
-static u_int8_t
-bwx_read_1(struct alpha_busspace *space, size_t offset)
-{
-	struct bwx_space *bwx = (struct bwx_space *) space;
-	alpha_mb();
-	return ldbu(bwx->base + offset);
-}
-
-static u_int16_t
-bwx_read_2(struct alpha_busspace *space, size_t offset)
-{
-	struct bwx_space *bwx = (struct bwx_space *) space;
-	alpha_mb();
-	return ldwu(bwx->base + offset);
-}
-
-static u_int32_t
-bwx_read_4(struct alpha_busspace *space, size_t offset)
-{
-	struct bwx_space *bwx = (struct bwx_space *) space;
-	alpha_mb();
-	return ldl(bwx->base + offset);
-}
-
-static void
-bwx_write_1(struct alpha_busspace *space, size_t offset, u_int8_t data)
-{
-	struct bwx_space *bwx = (struct bwx_space *) space;
-	stb(bwx->base + offset, data);
-	alpha_mb();
-}
-
-static void
-bwx_write_2(struct alpha_busspace *space, size_t offset, u_int16_t data)
-{
-	struct bwx_space *bwx = (struct bwx_space *) space;
-	stw(bwx->base + offset, data);
-	alpha_mb();
-}
-
-static void
-bwx_write_4(struct alpha_busspace *space, size_t offset, u_int32_t data)
-{
-	struct bwx_space *bwx = (struct bwx_space *) space;
-	stl(bwx->base + offset, data);
-	alpha_mb();
-}
-
-static struct alpha_busspace_ops bwx_space_ops = {
-	bwx_read_1,
-	bwx_read_2,
-	bwx_read_4,
-
-	busspace_generic_read_multi_1,
-	busspace_generic_read_multi_2,
-	busspace_generic_read_multi_4,
-
-	busspace_generic_read_region_1,
-	busspace_generic_read_region_2,
-	busspace_generic_read_region_4,
-
-	bwx_write_1,
-	bwx_write_2,
-	bwx_write_4,
-
-	busspace_generic_write_multi_1,
-	busspace_generic_write_multi_2,
-	busspace_generic_write_multi_4,
-
-	busspace_generic_write_region_1,
-	busspace_generic_write_region_2,
-	busspace_generic_write_region_4,
-
-	busspace_generic_set_multi_1,
-	busspace_generic_set_multi_2,
-	busspace_generic_set_multi_4,
-    
-	busspace_generic_set_region_1,
-	busspace_generic_set_region_2,
-	busspace_generic_set_region_4,
-    
-	busspace_generic_copy_region_1,
-	busspace_generic_copy_region_2,
-	busspace_generic_copy_region_4,
-
-	busspace_generic_barrier,
-};
-
-void
-bwx_init_space(struct bwx_space *bwx, u_int64_t base)
-{
-	bwx->ops = &bwx_space_ops;
-	bwx->base = base;
-}
-
diff --git a/sys/alpha/pci/cia.c b/sys/alpha/pci/cia.c
deleted file mode 100644
index 3abb50f..0000000
--- a/sys/alpha/pci/cia.c
+++ /dev/null
@@ -1,580 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-/*-
- * Copyright (c) 1998 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
- * NASA Ames Research Center.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the NetBSD
- *	Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-/*-
- * Copyright (c) 1995, 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- * 
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- * 
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_cpu.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/malloc.h>
-#include <sys/module.h>
-#include <sys/mutex.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/proc.h>
-#include <sys/rman.h>
-#include <sys/interrupt.h>
-
-#include <alpha/pci/ciareg.h>
-#include <alpha/pci/ciavar.h>
-#include <alpha/isa/isavar.h>
-
-#include <machine/bwx.h>
-#include <machine/cpuconf.h>
-#include <machine/intr.h>
-#include <machine/intrcnt.h>
-#include <machine/md_var.h>
-#include <machine/resource.h>
-#include <machine/rpb.h>
-#include <machine/sgmap.h>
-#include <machine/swiz.h>
-
-#include <vm/vm.h>
-#include <vm/vm_page.h>
-
-#include "alphapci_if.h"
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	cia_devclass;
-static device_t		cia0;		/* XXX only one for now */
-static u_int32_t	cia_hae_mem;
-static int		cia_rev, cia_ispyxis, cia_config;
-
-struct cia_softc {
-	int		junk;		/* no softc */
-};
-
-#define CIA_SOFTC(dev)	(struct cia_softc*) device_get_softc(dev)
-
-static alpha_chipset_read_hae_t	cia_read_hae;
-static alpha_chipset_write_hae_t cia_write_hae;
-
-static alpha_chipset_t cia_bwx_chipset = {
-	cia_read_hae,
-	cia_write_hae,
-};
-static alpha_chipset_t cia_swiz_chipset = {
-	cia_read_hae,
-	cia_write_hae,
-};
-
-static u_int32_t
-cia_swiz_set_hae_mem(void *arg, u_int32_t pa)
-{
-	/* Only bother with region 1 */
-#define REG1 (7 << 29)
-	if ((cia_hae_mem & REG1) != (pa & REG1)) {
-		/*
-		 * Seems fairly paranoid but this is what Linux does...
-		 */
-		u_int32_t msb = pa & REG1;
-		register_t s;
-		
-		s = intr_disable();
-		cia_hae_mem = (cia_hae_mem & ~REG1) | msb;
-		REGVAL(CIA_CSR_HAE_MEM) = cia_hae_mem;
-		alpha_mb();
-		cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
-		intr_restore(s);
-	}
-	return pa & ~REG1;
-}
-
-static u_int64_t
-cia_read_hae(void)
-{
-	return cia_hae_mem & REG1;
-}
-
-static void
-cia_write_hae(u_int64_t hae)
-{
-	u_int32_t pa = hae;
-	cia_swiz_set_hae_mem(0, pa);
-}
-
-static int cia_probe(device_t dev);
-static int cia_attach(device_t dev);
-static int cia_setup_intr(device_t dev, device_t child,
-			  struct resource *irq, int flags,
-			  driver_intr_t *intr, void *arg, void **cookiep);
-static int cia_teardown_intr(device_t dev, device_t child,
-			     struct resource *irq, void *cookie);
-
-static device_method_t cia_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		cia_probe),
-	DEVMETHOD(device_attach,	cia_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_setup_intr,	cia_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	cia_teardown_intr),
-
-	{ 0, 0 }
-};
-
-static driver_t cia_driver = {
-	"cia",
-	cia_methods,
-	sizeof(struct cia_softc),
-};
-
-#define CIA_SGMAP_BASE		(8*1024*1024)
-#define CIA_SGMAP_SIZE		(8*1024*1024)
-#define	CIA_PYXIS_BUG_BASE	(128*1024*1024)
-#define	CIA_PYXIS_BUG_SIZE	(2*1024*1024)
-
-static void
-cia_sgmap_invalidate(void)
-{
-	REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL;
-	alpha_mb();
-}
-
-static void
-cia_sgmap_invalidate_pyxis(void)
-{
-	volatile u_int64_t dummy;
-	u_int32_t ctrl;
-	int i;
-	register_t s;
-
-	s = intr_disable();
-	
-	/*
-	 * Put the Pyxis into PCI loopback mode.
-	 */
-	alpha_mb();
-	ctrl = REGVAL(CIA_CSR_CTRL);
-	REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
-	alpha_mb();
-
-	/*
-	 * Now, read from PCI dense memory space at offset 128M (our
-	 * target window base), skipping 64k on each read.  This forces
-	 * S/G TLB misses.
-	 *
-	 * XXX Looks like the TLB entries are `not quite LRU'.  We need
-	 * XXX to read more times than there are actual tags!
-	 */
-	for (i = 0; i < CIA_TLB_NTAGS + 4; i++) {
-		dummy = *((volatile u_int64_t *)
-		    ALPHA_PHYS_TO_K0SEG(CIA_PCI_DENSE + CIA_PYXIS_BUG_BASE +
-		    (i * 65536)));
-	}
-
-	/*
-	 * Restore normal PCI operation.
-	 */
-	alpha_mb();
-	REGVAL(CIA_CSR_CTRL) = ctrl;
-	alpha_mb();
-
-	intr_restore(s);
-}
-
-static void
-cia_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
-{
-	u_int64_t *sgtable = arg;
-	int index = alpha_btop(ba - CIA_SGMAP_BASE);
-
-	if (pa) {
-		if (pa > (1L<<32))
-			panic("cia_sgmap_map: can't map address 0x%lx", pa);
-		sgtable[index] = ((pa >> 13) << 1) | 1;
-	} else {
-		sgtable[index] = 0;
-	}
-	alpha_mb();
-
-	if (cia_ispyxis)
-		cia_sgmap_invalidate_pyxis();
-	else
-		cia_sgmap_invalidate();
-}
-
-static void
-cia_init_sgmap(void)
-{
-	void *sgtable;
-
-	/*
-	 * First setup Window 0 to map 8Mb to 16Mb with an
-	 * sgmap. Allocate the map aligned to a 32k boundary.
-	 */
-	REGVAL(CIA_PCI_W0BASE) = (CIA_SGMAP_BASE
-				  | CIA_PCI_WnBASE_SG_EN
-				  | CIA_PCI_WnBASE_W_EN);
-	alpha_mb();
-
-	REGVAL(CIA_PCI_W0MASK) = CIA_PCI_WnMASK_8M;
-	alpha_mb();
-
-	sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
-			       0, (1L<<34),
-			       32*1024, (1L<<34));
-	if (!sgtable)
-		panic("cia_init_sgmap: can't allocate page table");
-	REGVAL(CIA_PCI_T0BASE) =
-		(pmap_kextract((vm_offset_t) sgtable) >> CIA_PCI_TnBASE_SHIFT);
-
-	chipset.sgmap = sgmap_map_create(CIA_SGMAP_BASE,
-					 CIA_SGMAP_BASE + CIA_SGMAP_SIZE - 1,
-					 cia_sgmap_map, sgtable);
-	chipset.pci_sgmap = NULL;
-	chipset.dmsize = 1UL * 1024UL * 1024UL * 1024UL;
-	chipset.dmoffset = 1UL * 1024UL * 1024UL * 1024UL;
-
-	if (cia_ispyxis) {
-		/*
-		 * Pyxis has broken TLB invalidate. We use the NetBSD
-		 * workaround of using another region to spill entries 
-		 * out of the TLB. The 'bug' region is 2Mb mapped at
-		 * 128Mb.
-		 */
-		int i;
-		vm_offset_t pa;
-		u_int64_t *bugtable;
-
-		REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE |
-		    CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN;
-		alpha_mb();
-
-		REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M;
-		alpha_mb();
-
-		bugtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
-				       0, (1L<<34),
-				       2*1024, (1L<<34));
-		if (!bugtable)
-			panic("cia_init_sgmap: can't allocate page table");
-		REGVAL(CIA_PCI_T2BASE) =
-			(pmap_kextract((vm_offset_t) bugtable)
-			 >> CIA_PCI_TnBASE_SHIFT);
-
-		pa = sgmap_overflow_page();
-		for (i = 0; i < alpha_btop(CIA_PYXIS_BUG_SIZE); i++)
-			bugtable[i] = ((pa >> 13) << 1) | 1;
-	}
-}
-
-void
-cia_init()
-{
-	static int initted = 0;
-	static union space {
-		struct bwx_space bwx;
-		struct swiz_space swiz;
-	} io_space, mem_space;
-
-	if (initted) return;
-	initted = 1;
-
-	if (chipset_bwx == 0) {
-		swiz_init_space(&io_space.swiz, KV(CIA_PCI_SIO1));
-		swiz_init_space_hae(&mem_space.swiz, KV(CIA_PCI_SMEM1),
-				    cia_swiz_set_hae_mem, 0);
-
-		chipset = cia_swiz_chipset;
-	} else {
-		bwx_init_space(&io_space.bwx, KV(CIA_EV56_BWIO));
-		bwx_init_space(&mem_space.bwx, KV(CIA_EV56_BWMEM));
-
-		chipset = cia_bwx_chipset;
-	}
-	cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
-
-	busspace_isa_io = (struct alpha_busspace *) &io_space;
-	busspace_isa_mem = (struct alpha_busspace *) &mem_space;
-
-	if (platform.pci_intr_init)
-		platform.pci_intr_init();
-}
-
-static int
-cia_probe(device_t dev)
-{
-	uintptr_t use_bwx = 1;
-	device_t child;
-
-	if (cia0)
-		return ENXIO;
-	cia0 = dev;
-	device_set_desc(dev, "2117x Core Logic chipset"); /* XXX */
-
-	isa_init_intr();
-
-	cia_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
-
-	/*
-	 * Determine if we have a Pyxis.  Only two systypes can
-	 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX)
-	 * and the DEC_ST550 systype (Miata).
-	 */
-	if ((hwrpb->rpb_type == ST_EB164 &&
-	     (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) ||
-	    hwrpb->rpb_type == ST_DEC_550)
-		cia_ispyxis = TRUE;
-	else
-		cia_ispyxis = FALSE;
-
-	cia_init_sgmap();
-
-	/*
-	 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register.
-	 */
-	if (cia_rev >= 2 || cia_ispyxis)
-		cia_config = REGVAL(CIA_CSR_CNFG);
-	else
-		cia_config = 0;
-
-	if ((alpha_implver() < ALPHA_IMPLVER_EV5) ||
-	    (alpha_amask(ALPHA_AMASK_BWX) != 0) ||
-	    (cia_config & CNFG_BWEN) == 0) {
-		use_bwx = 0;
-	} else {
-		use_bwx = 1;
-	}
-
-	if (cia_ispyxis) {
-		if (use_bwx == 0) {
-			printf("PYXIS but not BWX?\n");
-		}
-	}
-
-	child = device_add_child(dev, "pcib", 0);
-	chipset_bwx = use_bwx = (use_bwx == (uintptr_t) 1);
-	device_set_ivars(child, (void *)use_bwx);
-	return 0;
-}
-
-static int
-cia_attach(device_t dev)
-{
-	char* name;
-	int pass;
-
-	cia_init();
-
-	name = cia_ispyxis ? "Pyxis" : "ALCOR/ALCOR2";
-	if (cia_ispyxis) {
-		name = "Pyxis";
-		pass = cia_rev;
-	} else {
-		name = "ALCOR/ALCOR2";
-		pass = cia_rev+1;
-	}
-	printf("cia0: %s, pass %d\n", name, pass);
-	if (cia_config)
-		printf("cia0: extended capabilities: %b\n",
-		       cia_config, CIA_CSR_CNFG_BITS);
-
-#ifdef DEC_ST550
-	if (hwrpb->rpb_type == ST_DEC_550 &&
-	    (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
-		/*
-		 * Miata 1 systems have a bug: DMA cannot cross
-		 * an 8k boundary!  Make sure PCI read prefetching
-		 * is disabled on these chips.  Note that secondary
-		 * PCI busses don't have this problem, because of
-		 * the way PPBs handle PCI read requests.
-		 *
-		 * In the 21174 Technical Reference Manual, this is
-		 * actually documented as "Pyxis Pass 1", but apparently
-		 * there are chips that report themselves as "Pass 1"
-		 * which do not have the bug!  Miatas with the Cypress
-		 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
-		 * have the bug, so we use this check.
-		 *
-		 * XXX We also need to deal with this boundary constraint
-		 * XXX in the PCI bus 0 (and ISA) DMA tags, but some
-		 * XXX drivers are going to need to be changed first.
-		 */
-		u_int32_t ctrl;
-
-		/* XXX no bets... */
-		printf("cia0: WARNING: Pyxis pass 1 DMA bug; no bets...\n");
-
-		alpha_mb();
-		ctrl = REGVAL(CIA_CSR_CTRL);
-		ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
-		REGVAL(CIA_CSR_CTRL) = ctrl;
-		alpha_mb();
-	}
-#endif
-
-	if (!platform.iointr)	/* XXX */
-		set_iointr(alpha_dispatch_intr);
-
-	if (chipset_bwx) {
-		snprintf(chipset_type, sizeof(chipset_type), "cia/bwx");
-		chipset_bwx = 1;
-		chipset_ports = CIA_EV56_BWIO;
-		chipset_memory = CIA_EV56_BWMEM;
-		chipset_dense = CIA_PCI_DENSE;
-	} else {
-		snprintf(chipset_type, sizeof(chipset_type), "cia/swiz");
-		chipset_bwx = 0;
-		chipset_ports = CIA_PCI_SIO1;
-		chipset_memory = CIA_PCI_SMEM1;
-		chipset_dense = CIA_PCI_DENSE;
-		chipset_hae_mask = 7L << 29;
-	}
-
-	bus_generic_attach(dev);
-	return 0;
-}
-
-static void
-cia_disable_intr(uintptr_t vector)
-{
-	int irq;
-
-	irq = (vector - 0x900) >> 4;
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_disable(irq);
-	mtx_unlock_spin(&icu_lock);
-}
-
-static void
-cia_enable_intr(uintptr_t vector)
-{
-	int irq;
-
-	irq = (vector - 0x900) >> 4;
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_enable(irq);
-	mtx_unlock_spin(&icu_lock);
-}
-
-static int
-cia_setup_intr(device_t dev, device_t child,
-	       struct resource *irq, int flags,
-	       driver_intr_t *intr, void *arg, void **cookiep)
-{
-	int error, start;
-	
-	error = rman_activate_resource(irq);
-	if (error)
-		return error;
-	start = rman_get_start(irq);
-
-	error = alpha_setup_intr(
-			device_get_nameunit(child ? child : dev),
-			0x900 + (start << 4), intr, arg, flags, cookiep,
-			&intrcnt[INTRCNT_EB164_IRQ + start],
-			cia_disable_intr, cia_enable_intr);
-	if (error)
-		return error;
-
-	/* Enable PCI interrupt */
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_enable(start);
-	mtx_unlock_spin(&icu_lock);
-
-	device_printf(child, "interrupting at CIA irq %d\n", start);
-
-	return 0;
-}
-
-static int
-cia_teardown_intr(device_t dev, device_t child,
-		  struct resource *irq, void *cookie)
-{
-	alpha_teardown_intr(cookie);
-	return rman_deactivate_resource(irq);
-}
-
-DRIVER_MODULE(cia, root, cia_driver, cia_devclass, 0, 0);
diff --git a/sys/alpha/pci/cia_pci.c b/sys/alpha/pci/cia_pci.c
deleted file mode 100644
index 69fd4f3..0000000
--- a/sys/alpha/pci/cia_pci.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- */
-/*-
- * Copyright (c) 1998 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
- * NASA Ames Research Center.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the NetBSD
- *	Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-/*-
- * Copyright (c) 1995, 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- * 
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- * 
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <machine/md_var.h>
-#include <sys/rman.h>
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-#include <machine/cpuconf.h>
-#include <machine/bwx.h>
-#include <machine/swiz.h>
-
-#include <alpha/pci/ciareg.h>
-#include <alpha/pci/ciavar.h>
-#include <alpha/pci/pcibus.h>
-#include <alpha/isa/isavar.h>
-
-#include "alphapci_if.h"
-#include "pcib_if.h"
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	pcib_devclass;
-
-static int
-cia_pcib_probe(device_t dev)
-{
-	device_set_desc(dev, "2117x PCI host bus adapter");
-
-	pci_init_resources();
-	device_add_child(dev, "pci", 0);
-
-	return 0;
-}
-
-static int
-cia_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
-{
-	switch (which) {
-	case  PCIB_IVAR_BUS:
-		*result = 0;
-		return 0;
-	}
-	return ENOENT;
-}
-
-static void *
-cia_pcib_cvt_dense(device_t dev, vm_offset_t addr)
-{
-	addr &= 0xffffffffUL;
-	return (void *) KV(addr | CIA_PCI_DENSE);
-}
-
-static void *
-cia_pcib_cvt_bwx(device_t dev, vm_offset_t addr)
-{
-	if (chipset_bwx) {
-		addr &= 0xffffffffUL;
-		return (void *) KV(addr | CIA_EV56_BWMEM);
-	} else {
-		return 0;
-	}
-}
-
-static void
-cia_clear_abort(void)
-{
-	/*
-	 * Some (apparently-common) revisions of EB164 and AlphaStation
-	 * firmware do the Wrong thing with PCI master and target aborts,
-	 * which are caused by accesing the configuration space of devices
-	 * that don't exist (for example).
-	 *
-	 * To work around this, we clear the CIA error register's PCI
-	 * master and target abort bits before touching PCI configuration
-	 * space and check it afterwards.  If it indicates a master or target
-	 * abort, the device wasn't there so we return 0xffffffff.
-	 */
-	REGVAL(CIA_CSR_CIA_ERR) = CIA_ERR_RCVD_MAS_ABT|CIA_ERR_RCVD_TAR_ABT;
-	alpha_mb();
-	alpha_pal_draina();	
-}
-
-static int
-cia_check_abort(void)
-{
-	u_int32_t errbits;
-	int ba = 0;
-
-	alpha_pal_draina();	
-	alpha_mb();
-	errbits = REGVAL(CIA_CSR_CIA_ERR);
-	if (errbits & (CIA_ERR_RCVD_MAS_ABT|CIA_ERR_RCVD_TAR_ABT))
-		ba = 1;
-
-	if (errbits) {
-		REGVAL(CIA_CSR_CIA_ERR) = errbits;
-		alpha_mb();
-		alpha_pal_draina();
-	}
-
-	return ba;
-}
-
-#define CIA_BWX_CFGADDR(b, s, f, r)				\
-	KV(((b) ? CIA_EV56_BWCONF1 : CIA_EV56_BWCONF0)		\
-	   | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
-
-#define BWX_CFGREAD(b, s, f, r, width, type, op) do {	\
-	vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);	\
-	type data;					\
-	cia_clear_abort();				\
-	if (badaddr((caddr_t)va, width)) {		\
-		cia_check_abort();			\
-		return ~0;				\
-	}						\
-	data = op(va);					\
-	if (cia_check_abort())				\
-		return ~0;				\
-	return data;					\
-} while (0)
-
-#define BWX_CFGWRITE(b, s, f, r, data, width, type, op) do {	\
-	vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);		\
-	cia_clear_abort();					\
-	if (badaddr((caddr_t)va, width)) return;		\
-	op(va, data);						\
-	cia_check_abort();					\
-	return;							\
-} while (0)
-
-#define CIA_SWIZ_CFGOFF(b, s, f, r) \
-	(((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
-
-/*  when doing a type 1 pci configuration space access, we
- *  must set a bit in the CIA_CSR_CFG register & clear it 
- *  when we're done 
-*/
-
-#define CIA_TYPE1_SETUP(b,s,old_cfg) if((b)) {		\
-        do {						\
-		(s) = splhigh();			\
-		(old_cfg) = REGVAL(CIA_CSR_CFG);	\
-		alpha_mb();				\
-		REGVAL(CIA_CSR_CFG) = (old_cfg) | 0x1;	\
-		alpha_mb();				\
-        } while(0);					\
-}
-
-#define CIA_TYPE1_TEARDOWN(b,s,old_cfg) if((b)) {	\
-        do {						\
-		alpha_mb();				\
-		REGVAL(CIA_CSR_CFG) = (old_cfg);	\
-		alpha_mb();				\
-		splx((s));				\
-        } while(0);					\
-}
-
-/*
- * From NetBSD:
- * Some (apparently-common) revisions of EB164 and AlphaStation
- * firmware do the Wrong thing with PCI master and target aborts,
- * which are caused by accesing the configuration space of devices
- * that don't exist (for example).
- *
- * To work around this, we clear the CIA error register's PCI
- * master and target abort bits before touching PCI configuration
- * space and check it afterwards.  If it indicates a master or target
- * abort, the device wasn't there so we return ~0
- */
-
-
-#define SWIZ_CFGREAD(b, s, f, r, width, type) do {			     \
-	type val = ~0;							     \
-	int ipl = 0;							     \
-	u_int32_t old_cfg = 0, errbits;					     \
-	vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r);			     \
-	vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(CIA_PCI_CONF), off);    \
-	REGVAL(CIA_CSR_CIA_ERR) = CIA_ERR_RCVD_MAS_ABT|CIA_ERR_RCVD_TAR_ABT; \
-	alpha_mb();							     \
-	CIA_TYPE1_SETUP(b,ipl,old_cfg);					     \
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			     \
-		val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv));	     \
-	}								     \
-        CIA_TYPE1_TEARDOWN(b,ipl,old_cfg);				     \
-	errbits = REGVAL(CIA_CSR_CIA_ERR);				     \
-	if (errbits & (CIA_ERR_RCVD_MAS_ABT|CIA_ERR_RCVD_TAR_ABT))	     \
-		val = ~0;						     \
-	if (errbits) {							     \
-		REGVAL(CIA_CSR_CIA_ERR) = errbits;			     \
-		alpha_mb();						     \
-		alpha_pal_draina();					     \
-	}								     \
-        return val;							     \
-} while (0)
-
-#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) do {		  \
-	int ipl = 0;							  \
-	u_int32_t old_cfg = 0;						  \
-	vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r);			  \
-	vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(CIA_PCI_CONF), off); \
-	alpha_mb();							  \
-	CIA_TYPE1_SETUP(b,ipl,old_cfg);					  \
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			  \
-                SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data));	  \
-		alpha_wmb();						  \
-	}								  \
-        CIA_TYPE1_TEARDOWN(b,ipl,old_cfg);				  \
-	return;								  \
-} while (0)
-
-static u_int32_t
-cia_pcib_swiz_read_config(u_int b, u_int s, u_int f, u_int reg, int width)
-{
-	switch (width) {
-	case 1:
-		SWIZ_CFGREAD(b, s, f, reg, BYTE, u_int8_t);
-		break;
-	case 2:
-		SWIZ_CFGREAD(b, s, f, reg, WORD, u_int16_t);
-		break;
-	case 4:
-		SWIZ_CFGREAD(b, s, f, reg, LONG, u_int32_t);
-	}
-	return ~0;
-}
-
-static void
-cia_pcib_swiz_write_config(u_int b, u_int s, u_int f, u_int reg,
-			   u_int32_t val, int width)
-{
-	switch (width) {
-	case 1:
-		SWIZ_CFGWRITE(b, s, f, reg, val, BYTE, u_int8_t);
-		break;
-	case 2:
-		SWIZ_CFGWRITE(b, s, f, reg, val, WORD, u_int16_t);
-		break;
-	case 4:
-		SWIZ_CFGWRITE(b, s, f, reg, val, LONG, u_int32_t);
-	}
-}
-
-static u_int32_t
-cia_pcib_bwx_read_config(u_int b, u_int s, u_int f, u_int reg, int width)
-{
-	switch (width) {
-	case 1:
-		BWX_CFGREAD(b, s, f, reg, 1, u_int8_t, ldbu);
-		break;
-	case 2:
-		BWX_CFGREAD(b, s, f, reg, 2, u_int16_t, ldwu);
-		break;
-	case 4:
-		BWX_CFGREAD(b, s, f, reg, 4, u_int32_t, ldl);
-	}
-	return ~0;
-}
-
-static void
-cia_pcib_bwx_write_config(u_int b, u_int s, u_int f, u_int reg,
-			  u_int32_t val, u_int width)
-{
-	switch (width) {
-	case 1:
-		BWX_CFGWRITE(b, s, f, reg, val, 1, u_int8_t, stb);
-		break;
-	case 2:
-		BWX_CFGWRITE(b, s, f, reg, val, 2, u_int16_t, stw);
-		break;
-	case 4:
-		BWX_CFGWRITE(b, s, f, reg, val, 4, u_int32_t, stl);
-	}
-}
-
-static int
-cia_pcib_maxslots(device_t dev)
-{
-	return 31;
-}
-
-static u_int32_t
-cia_pcib_read_config(device_t dev, int b, int s, int f,
-		     int reg, int width)
-{
-	pcicfgregs cfg;
-
-	if ((reg == PCIR_INTLINE) && (width == 1) && 
-	     (platform.pci_intr_map != NULL)) {
-		cfg.bus = b;
-		cfg.slot = s;
-		cfg.func = f;
-		cfg.intline = 255;
-		cfg.intpin =
-		    cia_pcib_read_config(dev, b, s, f, PCIR_INTPIN, 1);
-		platform.pci_intr_map((void *)&cfg);
-		if (cfg.intline != 255)
-			return cfg.intline;
-	}
-
-	if (chipset_bwx)
-		return cia_pcib_bwx_read_config(b, s, f, reg, width);
-	else
-		return cia_pcib_swiz_read_config(b, s, f, reg, width);
-}
-
-static void
-cia_pcib_write_config(device_t dev, int b, int s, int f,
-		      int reg, u_int32_t val, int width)
-{
-	if (chipset_bwx)
-		cia_pcib_bwx_write_config(b, s, f, reg, val, width);
-	else
-		cia_pcib_swiz_write_config(b, s, f, reg, val, width);
-}
-
-static device_method_t cia_pcib_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		cia_pcib_probe),
-	DEVMETHOD(device_attach,	bus_generic_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_read_ivar,	cia_pcib_read_ivar),
-	DEVMETHOD(bus_alloc_resource,	alpha_pci_alloc_resource),
-	DEVMETHOD(bus_release_resource,	pci_release_resource),
-	DEVMETHOD(bus_activate_resource, pci_activate_resource),
-	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
-	DEVMETHOD(bus_setup_intr,	alpha_platform_pci_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	alpha_platform_pci_teardown_intr),
-
-	/* alphapci interface */
-	DEVMETHOD(alphapci_cvt_dense,	cia_pcib_cvt_dense),
-	DEVMETHOD(alphapci_cvt_bwx,	cia_pcib_cvt_bwx),
-
-	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,	cia_pcib_maxslots),
-	DEVMETHOD(pcib_read_config,	cia_pcib_read_config),
-	DEVMETHOD(pcib_write_config,	cia_pcib_write_config),
-	DEVMETHOD(pcib_route_interrupt,	alpha_pci_route_interrupt),
-
-	{ 0, 0 }
-};
-
-static driver_t cia_pcib_driver = {
-	"pcib",
-	cia_pcib_methods,
-	1,
-};
-
-DRIVER_MODULE(pcib, cia, cia_pcib_driver, pcib_devclass, 0, 0);
diff --git a/sys/alpha/pci/ciareg.h b/sys/alpha/pci/ciareg.h
deleted file mode 100644
index 4b5d153..0000000
--- a/sys/alpha/pci/ciareg.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/* $FreeBSD$ */
-/* $NetBSD: ciareg.h,v 1.22 1998/06/06 20:40:14 thorpej Exp $ */
-
-/*-
- * Copyright (c) 1995, 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Authors: Chris G. Demetriou, Jason R. Thorpe
- * 
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- * 
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-/*
- * 21171 Chipset registers and constants.
- *
- * Taken from EC-QE18B-TE.
- */
-
-#define	REGVAL(r)	(*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
-#define	REGVAL64(r)	(*(volatile u_int64_t *)ALPHA_PHYS_TO_K0SEG(r))
-
-/*
- * Base addresses
- */
-#define	CIA_PCI_SMEM1	0x8000000000UL
-#define	CIA_PCI_SMEM2	0x8400000000UL
-#define	CIA_PCI_SMEM3	0x8500000000UL
-#define	CIA_PCI_SIO1	0x8580000000UL
-#define	CIA_PCI_SIO2	0x85c0000000UL
-#define	CIA_PCI_DENSE	0x8600000000UL
-#define	CIA_PCI_CONF	0x8700000000UL
-#define	CIA_PCI_IACK	0x8720000000UL
-#define	CIA_CSRS	0x8740000000UL
-#define	CIA_PCI_MC_CSRS	0x8750000000UL
-#define	CIA_PCI_ATRANS	0x8760000000UL
-#define	CIA_PCI_TBIA	0x8760000100UL
-#define	CIA_EV56_BWMEM	0x8800000000UL
-#define	CIA_EV56_BWIO	0x8900000000UL
-#define	CIA_EV56_BWCONF0 0x8a00000000UL
-#define	CIA_EV56_BWCONF1 0x8b00000000UL
-
-#define	CIA_PCI_W0BASE	0x8760000400UL
-#define	CIA_PCI_W0MASK	0x8760000440UL
-#define	CIA_PCI_T0BASE	0x8760000480UL
-
-#define	CIA_PCI_W1BASE	0x8760000500UL
-#define	CIA_PCI_W1MASK	0x8760000540UL
-#define	CIA_PCI_T1BASE	0x8760000580UL
-
-#define	CIA_PCI_W2BASE	0x8760000600UL
-#define	CIA_PCI_W2MASK	0x8760000640UL
-#define	CIA_PCI_T2BASE	0x8760000680UL
-
-#define	CIA_PCI_W3BASE	0x8760000700UL
-#define	CIA_PCI_W3MASK	0x8760000740UL
-#define	CIA_PCI_T3BASE	0x8760000780UL
-
-#define	PYXIS_INT_REQ	0x87a0000000UL
-#define	PYXIS_INT_MASK	0x87a0000040UL
-#define	PYXIS_GPO	0x87a0000180UL
-
-/*
- * Values for CIA_PCI_TBIA
- */
-#define	CIA_PCI_TBIA_NOOP	0	/* no operation */
-#define	CIA_PCI_TBIA_LOCKED	1	/* invalidate and unlock locked tags */
-#define	CIA_PCI_TBIA_UNLOCKED	2	/* invalidate unlocked tags */
-#define	CIA_PCI_TBIA_ALL	3	/* invalidate and unlock all tags */
-
-#define	CIA_TLB_NTAGS		8	/* number of TLB entries */
-
-/*
- * Values for CIA_PCI_WnBASE
- */
-#define	CIA_PCI_WnBASE_W_BASE	0xfff00000
-#define	CIA_PCI_WnBASE_DAC_EN	0x00000008	/* W3BASE only */
-#define	CIA_PCI_WnBASE_MEMCS_EN	0x00000004	/* W0BASE only */
-#define	CIA_PCI_WnBASE_SG_EN	0x00000002
-#define	CIA_PCI_WnBASE_W_EN	0x00000001
-
-/*
- * Values for CIA_PCI_WnMASK
- */
-#define	CIA_PCI_WnMASK_W_MASK	0xfff00000
-#define	CIA_PCI_WnMASK_1M	0x00000000
-#define	CIA_PCI_WnMASK_2M	0x00100000
-#define	CIA_PCI_WnMASK_4M	0x00300000
-#define	CIA_PCI_WnMASK_8M	0x00700000
-#define	CIA_PCI_WnMASK_16M	0x00f00000
-#define	CIA_PCI_WnMASK_32M	0x01f00000
-#define	CIA_PCI_WnMASK_64M	0x03f00000
-#define	CIA_PCI_WnMASK_128M	0x07f00000
-#define	CIA_PCI_WnMASK_256M	0x0ff00000
-#define	CIA_PCI_WnMASK_512M	0x1ff00000
-#define	CIA_PCI_WnMASK_1G	0x3ff00000
-#define	CIA_PCI_WnMASK_2G	0x7ff00000
-#define	CIA_PCI_WnMASK_4G	0xfff00000
-
-/*
- * Values for CIA_PCI_TnBASE
- */
-#define	CIA_PCI_TnBASE_MASK	0xfffffff0
-#define	CIA_PCI_TnBASE_SHIFT	2
-
-/*
- * General CSRs
- */
-
-#define	CIA_CSR_REV	(CIA_CSRS + 0x80)
-
-#define		REV_MASK		0x000000ff
-#define		REV_ALT_MEM		0x00000100	/* not on Pyxis */
-
-#define		REV_PYXIS_ID_MASK	0x0000ff00
-#define		REV_PYXIS_ID_21174	0x00000100
-
-#define	CIA_CSR_CTRL	(CIA_CSRS + 0x100)
-
-#define		CTRL_RCI_EN		0x00000001
-#define		CTRL_PCI_LOCK_EN	0x00000002
-#define		CTRL_PCI_LOOP_EN	0x00000004
-#define		CTRL_FST_BB_EN		0x00000008
-#define		CTRL_PCI_MST_EN		0x00000010
-#define		CTRL_PCI_MEM_EN		0x00000020
-#define		CTRL_PCI_REQ64_EN	0x00000040
-#define		CTRL_PCI_ACK64_EN	0x00000080
-#define		CTRL_ADDR_PE_EN		0x00000100
-#define		CTRL_PERR_EN		0x00000200
-#define		CTRL_FILL_ERR_EN	0x00000400
-#define		CTRL_ECC_CHK_EN		0x00001000
-#define		CTRL_CACK_EN_PE		0x00002000
-#define		CTRL_CON_IDLE_BC	0x00004000
-#define		CTRL_CSR_IOA_BYPASS	0x00008000
-#define		CTRL_IO_FLUSHREQ_EN	0x00010000
-#define		CTRL_CPU_CLUSHREQ_EN	0x00020000
-#define		CTRL_ARB_EV5_EN		0x00040000
-#define		CTRL_EN_ARB_LINK	0x00080000
-#define		CTRL_RD_TYPE		0x00300000
-#define		CTRL_RL_TYPE		0x03000000
-#define		CTRL_RM_TYPE		0x30000000
-
-/* a.k.a. CIA_CSR_PYXIS_CTRL1 */
-#define	CIA_CSR_CNFG	(CIA_CSRS + 0x140)
-
-#define		CNFG_BWEN		0x00000001
-#define		CNFG_MWEN		0x00000010
-#define		CNFG_DWEN		0x00000020
-#define		CNFG_WLEN		0x00000100
-
-#define	CIA_CSR_CNFG_BITS	"\20\11WLEN\6DWEN\5MWEN\1BWEN"
-
-#define	CIA_CSR_HAE_MEM	(CIA_CSRS + 0x400)
-
-#define		HAE_MEM_REG1_START(x)	(((u_int32_t)(x) & 0xe0000000UL) << 0)
-#define		HAE_MEM_REG1_MASK	0x1fffffffUL
-#define		HAE_MEM_REG2_START(x)	(((u_int32_t)(x) & 0x0000f800UL) << 16)
-#define		HAE_MEM_REG2_MASK	0x07ffffffUL
-#define		HAE_MEM_REG3_START(x)	(((u_int32_t)(x) & 0x000000fcUL) << 24)
-#define		HAE_MEM_REG3_MASK	0x03ffffffUL
-
-#define	CIA_CSR_HAE_IO	(CIA_CSRS + 0x440)
-
-#define		HAE_IO_REG1_START(x)	0UL
-#define		HAE_IO_REG1_MASK	0x01ffffffUL
-#define		HAE_IO_REG2_START(x)	(((u_int32_t)(x) & 0xfe000000UL) << 0)
-#define		HAE_IO_REG2_MASK	0x01ffffffUL
-
-#define	CIA_CSR_CFG	(CIA_CSRS + 0x480)
-
-#define		CFG_CFG_MASK		0x00000003UL
-
-#define	CIA_CSR_CIA_ERR	(CIA_CSRS + 0x8200)
-
-#define		CIA_ERR_COR_ERR		  0x00000001
-#define		CIA_ERR_UN_COR_ERR	  0x00000002
-#define		CIA_ERR_CPU_PE		  0x00000004
-#define		CIA_ERR_MEM_NEM		  0x00000008
-#define		CIA_ERR_PCI_SERR	  0x00000010
-#define		CIA_ERR_PERR		  0x00000020
-#define		CIA_ERR_PCI_ADDR_PE	  0x00000040
-#define		CIA_ERR_RCVD_MAS_ABT	  0x00000080
-#define		CIA_ERR_RCVD_TAR_ABT	  0x00000100
-#define		CIA_ERR_PA_PTE_INV	  0x00000200
-#define		CIA_ERR_FROM_WRT_ERR	  0x00000400
-#define		CIA_ERR_IOA_TIMEOUT	  0x00000800
-#define		CIA_ERR_LOST_COR_ERR	  0x00010000
-#define		CIA_ERR_LOST_UN_COR_ERR	  0x00020000
-#define		CIA_ERR_LOST_CPU_PE	  0x00040000
-#define		CIA_ERR_LOST_MEM_NEM	  0x00080000
-#define		CIA_ERR_LOST_PERR	  0x00200000
-#define		CIA_ERR_LOST_PCI_ADDR_PE  0x00400000
-#define		CIA_ERR_LOST_RCVD_MAS_ABT 0x00800000
-#define		CIA_ERR_LOST_RCVD_TAR_ABT 0x01000000
-#define		CIA_ERR_LOST_PA_PTE_INV	  0x02000000
-#define		CIA_ERR_LOST_FROM_WRT_ERR 0x04000000
-#define		CIA_ERR_LOST_IOA_TIMEOUT  0x08000000
-#define		CIA_ERR_VALID		  0x80000000
diff --git a/sys/alpha/pci/ciavar.h b/sys/alpha/pci/ciavar.h
deleted file mode 100644
index 1e50032..0000000
--- a/sys/alpha/pci/ciavar.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-extern void cia_init(void);
-
diff --git a/sys/alpha/pci/irongate.c b/sys/alpha/pci/irongate.c
deleted file mode 100644
index 6092bd7..0000000
--- a/sys/alpha/pci/irongate.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*-
- * Copyright (c) 2000 Andrew Gallatin
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_cpu.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <sys/malloc.h>
-
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-#include <alpha/isa/isavar.h>
-#include <alpha/pci/irongatereg.h>
-#include <alpha/pci/irongatevar.h>
-
-#include <machine/bwx.h>
-#include <machine/cpuconf.h>
-#include <machine/intr.h>
-#include <machine/intrcnt.h>
-#include <machine/md_var.h>
-#include <machine/resource.h>
-#include <machine/rpb.h>
-#include <machine/sgmap.h>
-
-#include <vm/vm.h>
-#include <vm/vm_page.h>
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	irongate_devclass;
-static device_t		irongate0;		/* XXX only one for now */
-
-struct irongate_softc {
-	int		junk;		/* no softc */
-};
-
-#define IRONGATE_SOFTC(dev)	(struct irongate_softc*) device_get_softc(dev)
-
-static alpha_chipset_read_hae_t	irongate_read_hae;
-static alpha_chipset_write_hae_t irongate_write_hae;
-
-static alpha_chipset_t irongate_chipset = {
-	irongate_read_hae,
-	irongate_write_hae,
-};
-
-/* 
- * There doesn't appear to be an hae on this platform
- */
-
-
-static u_int64_t
-irongate_read_hae(void)
-{
-	return 0;  
-}
-
-static void
-irongate_write_hae(u_int64_t hae)
-{
-}
-
-static int irongate_probe(device_t dev);
-static int irongate_attach(device_t dev);
-
-static device_method_t irongate_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		irongate_probe),
-	DEVMETHOD(device_attach,	irongate_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,      bus_generic_print_child),
-	DEVMETHOD(bus_setup_intr,	isa_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	isa_teardown_intr),
-
-	{ 0, 0 }
-};
-
-static driver_t irongate_driver = {
-	"irongate",
-	irongate_methods,
-	sizeof(struct irongate_softc),
-};
-
-void
-irongate_init()
-{
-	static int initted = 0;
-	static struct bwx_space io_space, mem_space;
-
-	if (initted) return;
-	initted = 1;
-
-	chipset = irongate_chipset;
-
-	bwx_init_space(&io_space, KV(IRONGATE_IO));
-	bwx_init_space(&mem_space, KV(IRONGATE_MEM));
-
-	busspace_isa_io = (struct alpha_busspace *) &io_space;
-	busspace_isa_mem = (struct alpha_busspace *) &mem_space;
-
-	if (platform.pci_intr_init)
-		platform.pci_intr_init();
-}
-
-static int
-irongate_probe(device_t dev)
-{
-
-	if (irongate0)
-		return ENXIO;
-	irongate0 = dev;
-	device_set_desc(dev, "AMD 751 Core Logic chipset"); 
-	isa_init_intr();
-	device_add_child(dev, "pcib", 0);
-	return 0;
-}
-
-	
-
-static int
-irongate_attach(device_t dev)
-{
-	irongate_init();
-
-	if (!platform.iointr)	/* XXX */
-		set_iointr(alpha_dispatch_intr);
-
-	snprintf(chipset_type, sizeof(chipset_type), "irongate");
-	chipset_bwx = 1;
-
-	chipset_ports = IRONGATE_IO;
-	chipset_memory = IRONGATE_MEM;
-	chipset_dense = IRONGATE_MEM;
-	/* no s/g support in this chipset, must use bounce-buffers */
-	chipset.sgmap = NULL;	
-	chipset.pci_sgmap = NULL;
-	chipset.dmsize = 4UL * 1024UL * 1024UL * 1024UL;
-	chipset.dmoffset = 0;
-
-	bus_generic_attach(dev);
-
-	return 0;
-}
-
-DRIVER_MODULE(irongate, root, irongate_driver, irongate_devclass, 0, 0);
-
diff --git a/sys/alpha/pci/irongate_pci.c b/sys/alpha/pci/irongate_pci.c
deleted file mode 100644
index e3bdf69..0000000
--- a/sys/alpha/pci/irongate_pci.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*-
- * Copyright (c) 2000 Andrew Gallatin
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <machine/md_var.h>
-#include <machine/bwx.h>
-#include <sys/rman.h>
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-#include <alpha/pci/irongatereg.h>
-#include <alpha/pci/irongatevar.h>
-#include <alpha/pci/pcibus.h>
-
-#include "alphapci_if.h"
-#include "pcib_if.h"
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	pcib_devclass;
-
-static int
-irongate_pcib_probe(device_t dev)
-{
-
-	device_set_desc(dev, "AMD 751 PCI host bus adapter");
-
-	pci_init_resources();
-	device_add_child(dev, "pci", 0);
-
-	/*  
-	 * XXX  -- The SRM console doesn't properly initialize
-	 * the AcerLabs M1533C southbridge.  We must turn off 32-bit 
-	 * DMA support.
-	 */
-	if ((0x153310b9 == PCIB_READ_CONFIG(dev, 0, 7, 0,
-					    PCIR_DEVVENDOR, 4))) {
-		u_int8_t value = PCIB_READ_CONFIG(dev, 0, 7, 0, 0x42, 1);
-		value &= ~0x40;
-		PCIB_WRITE_CONFIG(dev, 0, 7, 0, 0x42, 0, 1);
-	}
-
-	return 0;
-}
-
-static int
-irongate_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
-{
-	switch (which) {
-	case  PCIB_IVAR_BUS:
-		*result = 0;
-		return 0;
-	}
-	return ENOENT;
-}
-
-static void *
-irongate_pcib_cvt_dense(device_t dev, vm_offset_t addr)
-{
-	addr &= 0xffffffffUL;
-	return (void *) KV(addr | IRONGATE_MEM);
-}
-
-static void *
-irongate_pcib_cvt_bwx(device_t dev, vm_offset_t addr)
-{
-	addr &= 0xffffffffUL;
-	return (void *) KV(addr | IRONGATE_MEM);
-}
-
-static int
-irongate_pcib_maxslots(device_t dev)
-{
-	return 31;
-}
-
-static void
-irongate_clear_abort(void)
-{
-	alpha_mb();
-	alpha_pal_draina();	
-}
-
-static int
-irongate_check_abort(void)
-{
-	alpha_pal_draina();	
-	alpha_mb();
-
-	return 0;
-}
-
-#define IRONGATE_CFGADDR(b, s, f, r)				\
-	KV(IRONGATE_CONF | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
-
-#define CFGREAD(b, s, f, r, width, type, op) do {	\
-        vm_offset_t va;					\
-	type data;					\
-	va = IRONGATE_CFGADDR(b, s, f, r);		\
-	irongate_clear_abort();				\
-	if (badaddr((caddr_t)va, width)) {		\
-		irongate_check_abort();			\
-		return ~0;				\
-	}						\
-	data = op(va);					\
-	if (irongate_check_abort())			\
-		return ~0;				\
-	return data;					\
-} while (0)
-
-#define CFGWRITE(b, s, f, r, data, width, op) do {	\
-        vm_offset_t va;					\
-	va = IRONGATE_CFGADDR(b, s, f, r);		\
-	irongate_clear_abort();				\
-	if (badaddr((caddr_t)va, width))		\
-		return;					\
-	op(va, data);					\
-	irongate_check_abort();				\
-} while (0)
-
-static u_int32_t
-irongate_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
-			  u_int reg, int width)
-{
-	switch (width) {
-	case 1:
-		CFGREAD(b, s, f, reg, 1, u_int8_t, ldbu);
-		break;
-	case 2:
-		CFGREAD(b, s, f, reg, 2, u_int16_t, ldwu);
-		break;
-	case 4:
-		CFGREAD(b, s, f, reg, 4, u_int32_t, ldl);
-	}
-	return ~0;
-}
-
-static void
-irongate_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
-			   u_int reg, u_int32_t val, int width)
-{
-	switch (width) {
-	case 1:
-		CFGWRITE(b, s, f, reg, val, 1, stb);
-		break;
-	case 2:
-		CFGWRITE(b, s, f, reg, val, 2, stw);
-		break;
-	case 4:
-		CFGWRITE(b, s, f, reg, val, 4, stl);
-	}
-}
-
-static device_method_t irongate_pcib_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		irongate_pcib_probe),
-	DEVMETHOD(device_attach,	bus_generic_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_read_ivar,	irongate_pcib_read_ivar),
-	DEVMETHOD(bus_alloc_resource,	alpha_pci_alloc_resource),
-	DEVMETHOD(bus_release_resource,	pci_release_resource),
-	DEVMETHOD(bus_activate_resource, pci_activate_resource),
-	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
-	DEVMETHOD(bus_setup_intr, 	bus_generic_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
-
-	/* alphapci interface */
-	DEVMETHOD(alphapci_cvt_dense,	irongate_pcib_cvt_dense),
-	DEVMETHOD(alphapci_cvt_bwx,	irongate_pcib_cvt_bwx),
-
-	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,	irongate_pcib_maxslots),
-	DEVMETHOD(pcib_read_config,	irongate_pcib_read_config),
-	DEVMETHOD(pcib_write_config,	irongate_pcib_write_config),
-	DEVMETHOD(pcib_route_interrupt,	alpha_pci_route_interrupt),
-
-	{ 0, 0 }
-};
-
-static driver_t irongate_pcib_driver = {
-	"pcib",
-	irongate_pcib_methods,
-	1,
-};
-
-DRIVER_MODULE(pcib, irongate, irongate_pcib_driver, pcib_devclass, 0, 0);
-
-
diff --git a/sys/alpha/pci/irongatereg.h b/sys/alpha/pci/irongatereg.h
deleted file mode 100644
index 0d10d15..0000000
--- a/sys/alpha/pci/irongatereg.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*-
- * Copyright (c) 2000 Andrew Gallatin
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * AMD-751 Chipset registers and constants.
- *
- */
-
-
-/*
- *   memory / i/o space macros
- *
- */
-
-#define IRONGATE_MEM	  	0x10000000000UL
-#define IRONGATE_IACK_SC	0x101F8000000UL
-#define IRONGATE_IO		0x101FC000000UL
-#define IRONGATE_CONF		0x101FE000000UL
diff --git a/sys/alpha/pci/irongatevar.h b/sys/alpha/pci/irongatevar.h
deleted file mode 100644
index 31012d9..0000000
--- a/sys/alpha/pci/irongatevar.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*-
- * Copyright (c) 2000 Andrew Gallatin
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-extern void irongate_init(void);
-
diff --git a/sys/alpha/pci/lca.c b/sys/alpha/pci/lca.c
deleted file mode 100644
index c631a93..0000000
--- a/sys/alpha/pci/lca.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <sys/proc.h>
-#include <sys/sched.h>
-
-#include <alpha/pci/lcareg.h>
-#include <alpha/pci/lcavar.h>
-#include <alpha/isa/isavar.h>
-
-#include <machine/cpuconf.h>
-#include <machine/intr.h>
-#include <machine/md_var.h>
-#include <machine/sgmap.h>
-#include <machine/swiz.h>
-
-#include <vm/vm.h>
-#include <vm/vm_page.h>
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	lca_devclass;
-static device_t		lca0;		/* XXX only one for now */
-
-struct lca_softc {
-	int		junk;
-};
-
-#define LCA_SOFTC(dev)	(struct lca_softc*) device_get_softc(dev)
-
-static alpha_chipset_read_hae_t	lca_read_hae;
-static alpha_chipset_write_hae_t lca_write_hae;
-
-static alpha_chipset_t lca_chipset = {
-	lca_read_hae,
-	lca_write_hae,
-};
-
-/*
- * The LCA HAE is write-only.  According to NetBSD, this is where it starts.
- */
-static u_int32_t	lca_hae_mem = 0x80000000;
-
-/*
- * The first 16Mb ignores the HAE.  The next 112Mb uses the HAE to set
- * the high bits of the PCI address.
- */
-#define REG1 (1UL << 24)
-
-static u_int32_t
-lca_set_hae_mem(void *arg, u_int32_t pa)
-{
-	int s; 
-	u_int32_t msb;
-	if(pa >= REG1){
-		msb = pa & 0xf8000000;
-		pa -= msb;
-		s = splhigh();
-                if (msb != lca_hae_mem) {
-			lca_hae_mem = msb;
-			REGVAL(LCA_IOC_HAE) = lca_hae_mem;
-			alpha_mb();
-			alpha_mb();
-		}
-		splx(s);
-	}
-	return pa;
-}
-
-static u_int64_t
-lca_read_hae(void)
-{
-	return lca_hae_mem & 0xf8000000;
-}
-
-static void
-lca_write_hae(u_int64_t hae)
-{
-	u_int32_t pa = hae;
-	lca_set_hae_mem(0, pa);
-}
-
-static int lca_probe(device_t dev);
-static int lca_attach(device_t dev);
-static device_method_t lca_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		lca_probe),
-	DEVMETHOD(device_attach,	lca_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_setup_intr,	isa_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	isa_teardown_intr),
-
-	{ 0, 0 }
-};
-
-static driver_t lca_driver = {
-	"lca",
-	lca_methods,
-	sizeof(struct lca_softc),
-};
-
-#define LCA_SGMAP_BASE		(8*1024*1024)
-#define LCA_SGMAP_SIZE		(8*1024*1024)
-
-static void
-lca_sgmap_invalidate(void)
-{
-	alpha_mb();
-	REGVAL(LCA_IOC_TBIA) = 0;
-	alpha_mb();
-}
-
-static void
-lca_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
-{
-	u_int64_t *sgtable = arg;
-	int index = alpha_btop(ba - LCA_SGMAP_BASE);
-
-	if (pa) {
-		if (pa > (1L<<32))
-			panic("lca_sgmap_map: can't map address 0x%lx", pa);
-		sgtable[index] = ((pa >> 13) << 1) | 1;
-	} else {
-		sgtable[index] = 0;
-	}
-	alpha_mb();
-	lca_sgmap_invalidate();
-}
-
-static void
-lca_init_sgmap(void)
-{
-	void *sgtable;
-
-	/*
-	 * First setup Window 0 to map 8Mb to 16Mb with an
-	 * sgmap. Allocate the map aligned to a 32 boundary.
-	 */
-	REGVAL64(LCA_IOC_W_BASE0) = LCA_SGMAP_BASE |
-		IOC_W_BASE_SG | IOC_W_BASE_WEN;
-	alpha_mb();
-
-	REGVAL64(LCA_IOC_W_MASK0) = IOC_W_MASK_8M;
-	alpha_mb();
-
-	sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
-			       0, (1L<<34),
-			       32*1024, (1L<<34));
-	if (!sgtable)
-		panic("lca_init_sgmap: can't allocate page table");
-	chipset.sgmap = sgmap_map_create(LCA_SGMAP_BASE,
-					 LCA_SGMAP_BASE + LCA_SGMAP_SIZE,
-					 lca_sgmap_map, sgtable);
-	chipset.pci_sgmap = NULL;
-	chipset.dmsize = 1UL * 1024UL * 1024UL * 1024UL;
-	chipset.dmoffset = 1UL * 1024UL * 1024UL * 1024UL;
-	
-	REGVAL64(LCA_IOC_W_T_BASE0) = pmap_kextract((vm_offset_t) sgtable);
-	alpha_mb();
-	REGVAL64(LCA_IOC_TB_ENA) = IOC_TB_ENA_TEN;
-	alpha_mb();
-	lca_sgmap_invalidate();
-}
-
-void
-lca_init()
-{
-	static int initted = 0;
-	static struct swiz_space io_space, mem_space;
-
-	if (initted) return;
-	initted = 1;
-
-	swiz_init_space(&io_space, KV(LCA_PCI_SIO));
-	swiz_init_space_hae(&mem_space, KV(LCA_PCI_SPARSE),
-			    lca_set_hae_mem, 0);
-
-	busspace_isa_io = (struct alpha_busspace *) &io_space;
-	busspace_isa_mem = (struct alpha_busspace *) &mem_space;
-
-	/* Type 0 PCI conf access. */
-	REGVAL64(LCA_IOC_CONF) = 0;
-
-	if (platform.pci_intr_init)
-		platform.pci_intr_init();
-
-	chipset = lca_chipset;
-}
-
-static void
-lca_machine_check(unsigned long mces, struct trapframe *framep,
-    unsigned long vector, unsigned long param);
-
-static void lca_cpu_idle (void);
-
-static int
-lca_probe(device_t dev)
-{
-	if (lca0)
-		return ENXIO;
-	lca0 = dev;
-	device_set_desc(dev, "21066 Core Logic chipset"); /* XXX */
-
-	isa_init_intr();
-	lca_init_sgmap();
-
-	platform.mcheck_handler = lca_machine_check;
-	platform.cpu_idle = lca_cpu_idle;
-
-	device_add_child(dev, "pcib", 0);
-
-	return 0;
-}
-
-static int
-lca_attach(device_t dev)
-{
-	lca_init();
-
-	set_iointr(alpha_dispatch_intr);
-
-	snprintf(chipset_type, sizeof(chipset_type), "lca");
-	chipset_bwx = 0;
-	chipset_ports = LCA_PCI_SIO;
-	chipset_memory = LCA_PCI_SPARSE;
-	chipset_dense = LCA_PCI_DENSE;
-	chipset_hae_mask = IOC_HAE_ADDREXT;
-
-	bus_generic_attach(dev);
-	return 0;
-}
-
-static void
-lca_machine_check(unsigned long mces, struct trapframe *framep,
-    unsigned long vector, unsigned long param)
-{
-	long stat0;
-
-	machine_check(mces, framep, vector, param);
-	/* clear error flags in IOC_STATUS0 register */
-	stat0 = REGVAL64(LCA_IOC_STAT0);
-	REGVAL64(LCA_IOC_STAT0) = stat0;
-}
-
-void
-lca_cpu_idle (void)
-{
-	/*
-	 * 0x0 =  1
-	 * 0x1 =  1.5
-	 * 0x2 =  2
-	 * 0x3 =  4
-	 * 0x4 =  8
-	 * 0x5 = 16
-	 */
-	long override = 0x0;
-	long primary = 0x5;
-	long dma_ovr = 1;
-	long intr_ovr = 1;
-
-	REGVAL64(LCA_PMR) =
-	    (dma_ovr << 7) | (intr_ovr << 6) | (override << 3) | primary;
-	if (sched_runnable()) {
-		REGVAL64(LCA_PMR) =
-		    (override << 3) | override;
-	}
-}
-
-DRIVER_MODULE(lca, root, lca_driver, lca_devclass, 0, 0);
-
diff --git a/sys/alpha/pci/lca_pci.c b/sys/alpha/pci/lca_pci.c
deleted file mode 100644
index 3b05e63..0000000
--- a/sys/alpha/pci/lca_pci.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPELCAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <sys/rman.h>
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-#include <machine/cpuconf.h>
-#include <machine/swiz.h>
-#include <machine/md_var.h>
-
-#include <alpha/pci/lcareg.h>
-#include <alpha/pci/lcavar.h>
-#include <alpha/pci/pcibus.h>
-#include <alpha/isa/isavar.h>
-
-#include "alphapci_if.h"
-#include "pcib_if.h"
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	pcib_devclass;
-
-static int
-lca_pcib_probe(device_t dev)
-{
-	device_set_desc(dev, "21066 PCI host bus adapter");
-
-	pci_init_resources();
-	device_add_child(dev, "pci", 0);
-
-	return 0;
-}
-
-static int
-lca_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
-{
-	if (which == PCIB_IVAR_BUS) {
-		*result = 0;
-		return 0;
-	}
-	return ENOENT;
-}
-
-static struct resource *
-lca_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
-			u_long start, u_long end, u_long count, u_int flags)
-{
-	struct resource *rv = NULL;
-
-	if (type == SYS_RES_IRQ)
-		rv = isa_alloc_intr(bus, child, start);
-	else
-		rv = alpha_pci_alloc_resource(bus, child, type, rid,
-		    start, end, count, flags);
-	if (rv != NULL)
-		rman_set_rid(rv, *rid);
-	return (rv);
-}
-
-static int
-lca_pcib_release_resource(device_t bus, device_t child, int type, int rid,
-			  struct resource *r)
-{
-	if (type == SYS_RES_IRQ)
-		return isa_release_intr(bus, child, r);
-	else
-		return pci_release_resource(bus, child, type, rid, r);
-}
-
-static void *
-lca_pcib_cvt_dense(device_t dev, vm_offset_t addr)
-{
-	addr &= 0xffffffffUL;
-	return (void *) KV(addr | LCA_PCI_DENSE);
-}
-
-static int
-lca_pcib_maxslots(device_t dev)
-{
-	return 15;
-}
-
-#define LCA_CFGOFF(b, s, f, r) \
-	((b) ? (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) \
-	 : ((1 << ((s) + 11)) | ((f) << 8) | (r)))
-
-#define LCA_TYPE1_SETUP(b,s) if ((b)) {		\
-        do {					\
-		(s) = splhigh();		\
-		alpha_mb();			\
-		REGVAL(LCA_IOC_CONF) = 1;	\
-		alpha_mb();			\
-        } while(0);				\
-}
-
-#define LCA_TYPE1_TEARDOWN(b,s) if ((b)) {	\
-        do {					\
-		alpha_mb();			\
-		REGVAL(LCA_IOC_CONF) = 0;	\
-		alpha_mb();			\
-		splx((s));			\
-        } while(0);				\
-}
-
-#define CFGREAD(b, s, f, r, width, type) do {				  \
-	type val = ~0;							  \
-	int ipl = 0;							  \
-	vm_offset_t off = LCA_CFGOFF(b, s, f, r);			  \
-	vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(LCA_PCI_CONF), off); \
-	alpha_mb();							  \
-	LCA_TYPE1_SETUP(b,ipl);						  \
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			  \
-		val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv));	  \
-	}								  \
-        LCA_TYPE1_TEARDOWN(b,ipl);					  \
-	return val;							  \
-} while (0)							
-
-#define CFGWRITE(b, s, f, r, data, width, type) do {			  \
-	int ipl = 0;							  \
-	vm_offset_t off = LCA_CFGOFF(b, s, f, r);			  \
-	vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(LCA_PCI_CONF), off); \
-	alpha_mb();							  \
-	LCA_TYPE1_SETUP(b,ipl);						  \
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			  \
-                SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data));	  \
-		alpha_wmb();						  \
-	}								  \
-        LCA_TYPE1_TEARDOWN(b,ipl);					  \
-	return;								  \
-} while (0)
-
-u_int32_t
-lca_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
-		     u_int reg, int width)
-{
-
-	if ((reg == PCIR_INTLINE) && (width == 1)) {
-		/* SRM left bad value; let intr_route fill them in later */
-		return ~0;
-	}
-
-	switch (width) {
-	case 1:
-		CFGREAD(b, s, f, reg, BYTE, u_int8_t);
-		break;
-	case 2:
-		CFGREAD(b, s, f, reg, WORD, u_int16_t);
-		break;
-	case 4:
-		CFGREAD(b, s, f, reg, LONG, u_int32_t);
-	}
-	return ~0;
-}
-
-static void
-lca_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
-		      u_int reg, u_int32_t val, int width)
-{
-	switch (width) {
-	case 1:
-		CFGWRITE(b, s, f, reg, val, BYTE, u_int8_t);
-		break;
-	case 2:
-		CFGWRITE(b, s, f, reg, val, WORD, u_int16_t);
-		break;
-	case 4:
-		CFGWRITE(b, s, f, reg, val, LONG, u_int32_t);
-	}
-}
-
-static device_method_t lca_pcib_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		lca_pcib_probe),
-	DEVMETHOD(device_attach,	bus_generic_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_read_ivar,	lca_pcib_read_ivar),
-	DEVMETHOD(bus_alloc_resource,	lca_pcib_alloc_resource),
-	DEVMETHOD(bus_release_resource,	lca_pcib_release_resource),
-	DEVMETHOD(bus_activate_resource, pci_activate_resource),
-	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
-	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
-
-	/* alphapci interface */
-	DEVMETHOD(alphapci_cvt_dense,	lca_pcib_cvt_dense),
-
-	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,	lca_pcib_maxslots),
-	DEVMETHOD(pcib_read_config,	lca_pcib_read_config),
-	DEVMETHOD(pcib_write_config,	lca_pcib_write_config),
-	DEVMETHOD(pcib_route_interrupt,	alpha_pci_route_interrupt),
-
-	{ 0, 0 }
-};
-
-static driver_t lca_pcib_driver = {
-	"pcib",
-	lca_pcib_methods,
-	1,
-};
-
-DRIVER_MODULE(pcib, lca, lca_pcib_driver, pcib_devclass, 0, 0);
diff --git a/sys/alpha/pci/lcareg.h b/sys/alpha/pci/lcareg.h
deleted file mode 100644
index c6255d8..0000000
--- a/sys/alpha/pci/lcareg.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* $FreeBSD$ */
-/* $NetBSD: lcareg.h,v 1.8 1997/09/05 02:14:31 thorpej Exp $ */
-
-/*-
- * Copyright (c) 1995 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Authors: Jeffrey Hsu, Jason R. Thorpe
- * 
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- * 
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-/*
- * 21066 chip registers
- */
-
-#define REGVAL(r)	(*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
-#define REGVAL64(r)	(*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r))
-
-/*
- * Base addresses
- */
-#define LCA_IOC_BASE	0x180000000L		/* LCA IOC Regs */
-#define LCA_PCI_SIO	0x1c0000000L		/* PCI Sp. I/O Space */
-#define LCA_PCI_CONF	0x1e0000000L		/* PCI Conf. Space */
-#define LCA_PCI_SPARSE	0x200000000L		/* PCI Sparse Space */
-#define LCA_PCI_DENSE	0x300000000L		/* PCI Dense Space */
-
-#define LCA_PMR		0x120000098L		/* Power Management (21066A)*/
-
-#define LCA_IOC_HAE	LCA_IOC_BASE		/* Host Address Ext. (64) */
-#define	IOC_HAE_ADDREXT	0x00000000f8000000UL
-#define	IOC_HAE_RSVSD	0xffffffff07ffffffUL
-
-#define LCA_IOC_CONF	(LCA_IOC_BASE + 0x020)	/* Configuration Cycle Type */
-
-#define LCA_IOC_STAT0	(LCA_IOC_BASE + 0x040)	/* Status 0 */
-#define	IOC_STAT0_CMD	0x000000000000000fUL	/* PCI command mask */
-#define	IOC_STAT0_ERR	0x0000000000000010UL	/* IOC error indicator R/W1C */
-#define	IOC_STAT0_LOST	0x0000000000000020UL	/* IOC lose error info R/W1C */
-#define	IOC_STAT0_THIT	0x0000000000000040UL	/* test hit */
-#define	IOC_STAT0_TREF	0x0000000000000080UL	/* test reference */
-#define	IOC_STAT0_CODE	0x0000000000000700UL	/* code mask */
-#define	IOC_STAT0_CODESHIFT 8
-#define	IOC_STAT0_P_NBR	0x00000000ffffe000UL	/* page number mask */
-
-#define LCA_IOC_STAT1	(LCA_IOC_BASE + 0x060)	/* Status 1 */
-#define	IOC_STAT1_ADDR	0x00000000ffffffffUL	/* PCI address mask */
-
-#define	LCA_IOC_TBIA	(LCA_IOC_BASE + 0x080)	/* TLB Invalidate All */
-#define	LCA_IOC_TB_ENA	(LCA_IOC_BASE + 0x0a0)	/* TLB Enable */
-#define	IOC_TB_ENA_TEN	0x0000000000000080UL
-
-#define LCA_IOC_W_BASE0	(LCA_IOC_BASE + 0x100)	/* Window Base */
-#define LCA_IOC_W_MASK0	(LCA_IOC_BASE + 0x140)	/* Window Mask */
-#define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */
-
-#define LCA_IOC_W_BASE1	(LCA_IOC_BASE + 0x120)	/* Window Base */
-#define LCA_IOC_W_MASK1	(LCA_IOC_BASE + 0x160)	/* Window Mask */
-#define LCA_IOC_W_T_BASE1 (LCA_IOC_BASE + 0x1a0) /* Translated Base */
-
-#define	IOC_W_BASE_W_BASE 0x00000000fff00000UL	/* Window base value */
-#define	IOC_W_BASE_SG	  0x0000000100000000UL	/* Window uses SGMAPs */
-#define	IOC_W_BASE_WEN	  0x0000000200000000UL	/* Window enable */
-
-#define	IOC_W_MASK_1M	0x0000000000000000UL	/* 1MB window */
-#define	IOC_W_MASK_2M	0x0000000000100000UL	/* 2MB window */
-#define	IOC_W_MASK_4M	0x0000000000300000UL	/* 4MB window */
-#define	IOC_W_MASK_8M	0x0000000000700000UL	/* 8MB window */
-#define	IOC_W_MASK_16M	0x0000000000f00000UL	/* 16MB window */
-#define	IOC_W_MASK_32M	0x0000000001f00000UL	/* 32MB window */
-#define	IOC_W_MASK_64M	0x0000000003f00000UL	/* 64MB window */
-#define	IOC_W_MASK_128M	0x0000000007f00000UL	/* 128M window */
-#define	IOC_W_MASK_256M	0x000000000ff00000UL	/* 256M window */
-#define	IOC_W_MASK_512M	0x000000001ff00000UL	/* 512M window */
-#define	IOC_W_MASK_1G	0x000000003ff00000UL	/* 1GB window */
-#define	IOC_W_MASK_2G	0x000000007ff00000UL	/* 2GB window */
-#define	IOC_W_MASK_4G	0x00000000fff00000UL	/* 4GB window */
-
-#define	IOC_W_T_BASE	0x00000000fffffc00UL	/* page table base */
diff --git a/sys/alpha/pci/lcavar.h b/sys/alpha/pci/lcavar.h
deleted file mode 100644
index ee53b75..0000000
--- a/sys/alpha/pci/lcavar.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-struct device;
-
-extern void lca_init(void);
-u_int32_t lca_pcib_read_config(struct device *dev, u_int b, u_int s, u_int f,
-			       u_int reg, int width);
diff --git a/sys/alpha/pci/pci_eb164_intr.s b/sys/alpha/pci/pci_eb164_intr.s
deleted file mode 100644
index 542839f..0000000
--- a/sys/alpha/pci/pci_eb164_intr.s
+++ /dev/null
@@ -1,95 +0,0 @@
-/* $FreeBSD$ */
-/* $NetBSD: pci_eb164_intr.s,v 1.5 1997/09/02 13:19:42 thorpej Exp $ */
-
-/*-
- * Copyright (c) 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- * 
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- * 
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-/*
- * The description of how to enable and disable interrupts in the
- * AlphaPC 164 motherboard technical reference manual is incorrect,
- * at least for the OSF/1 PALcode.
- *
- * These functions were written by disassembling a Digital UNIX kernel's
- * eb164_intrdsabl and eb164_intrenabl functions (because they had
- * interesting names), and then playing with them to see how to call
- * them correctly.
- *
- * It looks like the right thing to do is to call them with the interrupt
- * request that you want to enable or disable (presumably in the range
- * 0 -> 23, since there are 3 8-bit interrupt-enable bits in the
- * interrupt mask PLD).
- */
-
-#include <machine/asm.h>
-
-__KERNEL_RCSID(0, "$NetBSD: pci_eb164_intr.s,v 1.5 1997/09/02 13:19:42 thorpej Exp $");
-
-	.text
-LEAF(eb164_intr_enable,1)
-	mov	a0, a1
-	ldiq	a0, 0x34
-	call_pal PAL_cserve
-	RET
-	END(eb164_intr_enable)
-
-	.text
-LEAF(eb164_intr_disable,1)
-	mov	a0, a1
-	ldiq	a0, 0x35
-	call_pal PAL_cserve
-	RET
-	END(eb164_intr_disable)
-
-	.text
-LEAF(eb164_intr_enable_icsr,1)
-	mov	a0, a1
-	ldiq	a0, 0x34
-	call_pal PAL_cserve
-	ldiq	a0, 0x08	/* Allow PALRES */
-	call_pal PAL_cserve
-	.long	0x66100118	/* hw_mfpr a0, icsr */
-	ldah	a1, 0x0020	/* IMSK1 */
-	or	a0, a1, a0
-	xor	a0, a1, a0
-	.long	0x76100118	/* hw_mtpr a0, icsr */
-	ldiq	a0, 0x09	/* Disable PALRES */
-	call_pal PAL_cserve
-	RET
-	END(eb164_intr_enable_icsr)
-
-	.text
-LEAF(eb164_intr_disable_icsr,1)
-	ldiq	a0, 0x08	/* Allow PALRES */
-	call_pal PAL_cserve
-	.long	0x66100118	/* hw_mfpr a0, icsr */
-	ldah	a1, 0x0020	/* IMSK1 */
-	or	a0, a1, a0
-	.long	0x76100118	/* hw_mtpr a0, icsr */
-	ldiq	a0, 0x09	/* Disable PALRES */
-	call_pal PAL_cserve
-	RET
-	END(eb164_intr_disable_icsr)
diff --git a/sys/alpha/pci/pci_eb64plus_intr.s b/sys/alpha/pci/pci_eb64plus_intr.s
deleted file mode 100644
index ce33c2a..0000000
--- a/sys/alpha/pci/pci_eb64plus_intr.s
+++ /dev/null
@@ -1,64 +0,0 @@
-/* $FreeBSD$ */
-/* $NetBSD: pci_eb64plus_intr.s,v 1.2 1997/09/02 13:19:43 thorpej Exp $ */
-
-/*-
- * Copyright (c) 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- * 
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- * 
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-/*
- * This file hacked from pci_eb164_intr.s
- *
- * These functions were written by disassembling a Digital UNIX kernel's
- * eb64p_intrdsabl and eb64p_intrenabl functions (because they had
- * interesting names, and looked like the eb164 versions which were
- * known to already work), and then playing with them to see how to call
- * them correctly.
- *
- * It looks like the right thing to do is to call them with the interrupt
- * request that you want to enable or disable (presumably in the range
- * 0 -> 23, since there are 3 8-bit interrupt-enable bits in the
- * interrupt mask PLD).
- */
-
-#include <machine/asm.h>
-
-__KERNEL_RCSID(0, "$NetBSD: pci_eb64plus_intr.s,v 1.2 1997/09/02 13:19:43 thorpej Exp $");
-
-	.text
-LEAF(eb64plus_intr_enable,1)
-	mov	a0, a1
-	ldiq	a0, 0x34
-	call_pal PAL_cserve
-	RET
-	END(eb64plus_intr_enable)
-
-	.text
-LEAF(eb64plus_intr_disable,1)
-	mov	a0, a1
-	ldiq	a0, 0x35
-	call_pal PAL_cserve
-	RET
-	END(eb64plus_intr_disable)
diff --git a/sys/alpha/pci/pcibus.c b/sys/alpha/pci/pcibus.c
deleted file mode 100644
index 61c6bd7..0000000
--- a/sys/alpha/pci/pcibus.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/*-
- * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice unmodified, this list of conditions, and the following
- *    disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_isa.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/proc.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/interrupt.h>
-#include <sys/sysctl.h>
-#include <sys/rman.h>
-
-#include <dev/pci/pcivar.h>
-#include <machine/chipset.h>
-#include <machine/cpuconf.h>
-#include <machine/resource.h>
-#include <machine/md_var.h>
-#include <alpha/pci/pcibus.h>
-#include <alpha/isa/isavar.h>
-
-#include "alphapci_if.h"
-
-#define	ISA_IRQ_OFFSET	0xe0
-#define	ISA_IRQ_LEN	0x10
-
-struct alpha_busspace *busspace_isa_io;
-struct alpha_busspace *busspace_isa_mem;
-
-char chipset_type[10];
-int chipset_bwx = 0;
-long chipset_ports = 0;
-long chipset_memory = 0;
-long chipset_dense = 0;
-long chipset_hae_mask = 0;
-
-SYSCTL_NODE(_hw, OID_AUTO, chipset, CTLFLAG_RW, 0, "PCI chipset information");
-SYSCTL_STRING(_hw_chipset, OID_AUTO, type, CTLFLAG_RD, chipset_type, 0,
-	      "PCI chipset type");
-SYSCTL_INT(_hw_chipset, OID_AUTO, bwx, CTLFLAG_RD, &chipset_bwx, 0,
-	   "PCI chipset supports BWX access");
-SYSCTL_LONG(_hw_chipset, OID_AUTO, ports, CTLFLAG_RD, &chipset_ports, 0,
-	    "PCI chipset port address");
-SYSCTL_LONG(_hw_chipset, OID_AUTO, memory, CTLFLAG_RD, &chipset_memory, 0,
-	    "PCI chipset memory address");
-SYSCTL_LONG(_hw_chipset, OID_AUTO, dense, CTLFLAG_RD, &chipset_dense, 0,
-	    "PCI chipset dense memory address");
-SYSCTL_LONG(_hw_chipset, OID_AUTO, hae_mask, CTLFLAG_RD, &chipset_hae_mask, 0,
-	    "PCI chipset mask for HAE register");
-
-int
-alpha_pci_route_interrupt(device_t bus, device_t dev, int pin)
-{
-	/*
-	 * Validate requested pin number.
-	 */
-	if ((pin < 1) || (pin > 4))
-		return(255);
-	
-	if (platform.pci_intr_route)
-		return(platform.pci_intr_route(bus, dev, pin));
-	return(255);
-}
-
-#ifdef DEV_ISA
-struct resource *
-alpha_platform_alloc_ide_intr(int chan)
-{
-	int irqs[2] = { 14, 15 };
-	return (isa_alloc_intr(0, 0, irqs[chan]));
-}
-
-int
-alpha_platform_release_ide_intr(int chan, struct resource *res)
-{
-	return isa_release_intr(0, 0, res);
-}
-
-int
-alpha_platform_setup_ide_intr(device_t dev,
-			      struct resource *res,
-			      driver_intr_t *fn, void *arg,
-			      void **cookiep)
-{
-	return isa_setup_intr(0, dev, res, INTR_TYPE_BIO, fn, arg, cookiep);
-}
-
-int
-alpha_platform_teardown_ide_intr(device_t dev,
-				 struct resource *res, void *cookie)
-{
-	return isa_teardown_intr(0, dev, res, cookie);
-}
-#else
-struct resource *
-alpha_platform_alloc_ide_intr(int chan)
-{
-	return (NULL);
-}
-int
-alpha_platform_release_ide_intr(int chan, struct resource *res)
-{
-	return (ENXIO);
-}
-
-int
-alpha_platform_setup_ide_intr(struct resource *res,
-    driver_intr_t *fn, void *arg, void **cookiep)
-{
-	return (ENXIO);
-}
-
-int
-alpha_platform_teardown_ide_intr(struct resource *res, void *cookie)
-{
-	return (ENXIO);
-}
-#endif
-
-static struct rman irq_rman, port_rman, mem_rman;
-
-int
-alpha_platform_pci_setup_intr(device_t dev, device_t child,
-			      struct resource *irq,  int flags,
-			      driver_intr_t *intr, void *arg,
-			      void **cookiep)
-{
-#ifdef DEV_ISA
-	/*
-	 * XXX - If we aren't the resource manager for this IRQ, assume that
-	 * it is actually handled by the ISA PIC.
-	 */
-	if (!rman_is_region_manager(irq, &irq_rman))
-		return isa_setup_intr(dev, child, irq, flags, intr, arg,
-				      cookiep);
-	else
-#endif
-		return bus_generic_setup_intr(dev, child, irq, flags, intr,
-					      arg, cookiep);
-}
-
-int
-alpha_platform_pci_teardown_intr(device_t dev, device_t child,
-				 struct resource *irq, void *cookie)
-{
-#ifdef DEV_ISA
-	/*
-	 * XXX - If we aren't the resource manager for this IRQ, assume that
-	 * it is actually handled by the ISA PIC.
-	 */
-	if (!rman_is_region_manager(irq, &irq_rman))
-		return isa_teardown_intr(dev, child, irq, cookie);
-	else
-#endif
-		return bus_generic_teardown_intr(dev, child, irq, cookie);
-}
-
-void 
-pci_init_resources(void)
-{
-	irq_rman.rm_start = 0;
-	irq_rman.rm_end = 65536;
-	irq_rman.rm_type = RMAN_ARRAY;
-	irq_rman.rm_descr = "PCI Mapped Interrupts";
-	if (rman_init(&irq_rman)
-	    || rman_manage_region(&irq_rman, 0, 65536))
-		panic("pci_init_resources irq_rman");
-
-	port_rman.rm_start = 0;
-	port_rman.rm_end = ~0u;
-	port_rman.rm_type = RMAN_ARRAY;
-	port_rman.rm_descr = "I/O ports";
-	if (rman_init(&port_rman)
-	    || rman_manage_region(&port_rman, 0x0, (1L << 32)))
-		panic("pci_init_resources port_rman");
-
-	mem_rman.rm_start = 0;
-	mem_rman.rm_end = ~0u;
-	mem_rman.rm_type = RMAN_ARRAY;
-	mem_rman.rm_descr = "I/O memory";
-	if (rman_init(&mem_rman)
-	    || rman_manage_region(&mem_rman, 0x0, (1L << 32)))
-		panic("pci_init_resources mem_rman");
-}
-
-/*
- * Allocate a resource on behalf of child.  NB: child is usually going to be a
- * child of one of our descendants, not a direct child of the pci chipset.
- */
-struct resource *
-alpha_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		   u_long start, u_long end, u_long count, u_int flags)
-{
-	struct	rman *rm;
-	struct	resource *rv;
-	void *va;
-	int rstart;
-
-	switch (type) {
-	case SYS_RES_IRQ:
-#ifdef DEV_ISA
-		if((start >= ISA_IRQ_OFFSET) &&
-		   (end < ISA_IRQ_OFFSET + ISA_IRQ_LEN)) {
-		  	rv = isa_alloc_intrs(bus, child,
-			    start - ISA_IRQ_OFFSET, end - ISA_IRQ_OFFSET);
-			if (rv != NULL)
-				rman_set_rid(rv, *rid);
-			return (rv);
-		}
-		else
-#endif
-			rm = &irq_rman;
-		break;
-
-	case SYS_RES_IOPORT:
-	case SYS_RES_MEMORY:
-		rm = ALPHAPCI_GET_RMAN(bus, type);
-		break;
-
-	default:
-		return 0;
-	}
-
-	rv = rman_reserve_resource(rm, start, end, count, flags, child);
-	if (rv == 0)
-		return 0;
-
-	rman_set_rid(rv, *rid);
-	rstart = rman_get_start(rv);
-	rman_set_bustag(rv, ALPHAPCI_GET_BUSTAG(bus, type));
-	rman_set_bushandle(rv, rstart);
-	switch (type) {
-	case SYS_RES_MEMORY:
-		va = 0;
-		if (flags & PCI_RF_DENSE)
-			va = ALPHAPCI_CVT_DENSE(bus, rstart);
-		else if (flags & PCI_RF_BWX)
-			va = ALPHAPCI_CVT_BWX(bus, rstart);
-		else
-			va = (void *)ALPHA_PHYS_TO_K0SEG(rstart);
-		rman_set_virtual(rv, va);
-
-		break;
-	}
-
-	return rv;
-}
-
-int
-pci_activate_resource(device_t bus, device_t child, int type, int rid,
-		      struct resource *r)
-{
-	return (rman_activate_resource(r));
-}
-
-int
-pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
-			  struct resource *r)
-{
-	return (rman_deactivate_resource(r));
-}
-
-int
-pci_release_resource(device_t bus, device_t child, int type, int rid,
-		       struct resource *r)
-{
-	return (rman_release_resource(r));
-}
-
-struct alpha_busspace *
-pci_get_bustag(device_t dev, int type)
-{
-	switch (type) {
-	case SYS_RES_IOPORT:
-		return busspace_isa_io;
-
-	case SYS_RES_MEMORY:
-		return busspace_isa_mem;
-	}
-
-	return 0;
-}
-
-struct rman *
-pci_get_rman(device_t dev, int type)
-{
-	switch (type) {
-	case SYS_RES_IOPORT:
-		return &port_rman;
-
-	case SYS_RES_MEMORY:
-		return &mem_rman;
-	}
-
-	return 0;
-}
-
-#include "opt_ddb.h"
-#ifdef DDB
-#include <ddb/ddb.h>
-
-DB_COMMAND(in, db_in)
-{
-    int c;
-    int size;
-
-    if (!have_addr)
-	return;
-
-    size = -1;
-    while ((c = *modif++) != '\0') {
-	switch (c) {
-	case 'b':
-	    size = 1;
-	    break;
-	case 'w':
-	    size = 2;
-	    break;
-	case 'l':
-	    size = 4;
-	    break;
-	}
-    }
-
-    if (size < 0) {
-	db_printf("bad size\n");
-	return;
-    }
-
-    if (count <= 0) count = 1;
-    while (--count >= 0) {
-	db_printf("%08lx:\t", addr);
-	switch (size) {
-	case 1:
-	    db_printf("%02x\n", inb(addr));
-	    break;
-	case 2:
-	    db_printf("%04x\n", inw(addr));
-	    break;
-	case 4:
-	    db_printf("%08x\n", inl(addr));
-	    break;
-	}
-    }
-}
-
-#endif
diff --git a/sys/alpha/pci/pcibus.h b/sys/alpha/pci/pcibus.h
deleted file mode 100644
index 608b2a5..0000000
--- a/sys/alpha/pci/pcibus.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*-
- * Copyright (c) 1998 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-void pci_init_resources(void);
-struct resource *alpha_pci_alloc_resource(device_t bus, device_t child,
-				    int type, int *rid,
-				    u_long start, u_long end, u_long count,
-				    u_int flags);
-int pci_activate_resource(device_t bus, device_t child, int type, int rid,
-			  struct resource *r);
-int pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
-			    struct resource *r);
-int pci_release_resource(device_t bus, device_t child, int type, int rid,
-			 struct resource *r);
-struct alpha_busspace *pci_get_bustag(device_t dev, int type);
-struct rman *pci_get_rman(device_t dev, int type);
diff --git a/sys/alpha/pci/swiz.c b/sys/alpha/pci/swiz.c
deleted file mode 100644
index fe25038..0000000
--- a/sys/alpha/pci/swiz.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*-
- * Copyright (c) 2000 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/kobj.h>
-
-#include <machine/bus.h>
-#include <machine/swiz.h>
-
-static u_int8_t
-swiz_read_1(struct alpha_busspace *space, size_t offset)
-{
-	struct swiz_space *swiz = (struct swiz_space *) space;
-	alpha_mb();
-	if (swiz->sethae)
-		offset = swiz->sethae(swiz->arg, offset);
-	return SPARSE_READ_BYTE(swiz->base, offset);
-}
-
-static u_int16_t
-swiz_read_2(struct alpha_busspace *space, size_t offset)
-{
-	struct swiz_space *swiz = (struct swiz_space *) space;
-	alpha_mb();
-	if (swiz->sethae)
-		offset = swiz->sethae(swiz->arg, offset);
-	return SPARSE_READ_WORD(swiz->base, offset);
-}
-
-static u_int32_t
-swiz_read_4(struct alpha_busspace *space, size_t offset)
-{
-	struct swiz_space *swiz = (struct swiz_space *) space;
-	alpha_mb();
-	if (swiz->sethae)
-		offset = swiz->sethae(swiz->arg, offset);
-	return SPARSE_READ_LONG(swiz->base, offset);
-}
-
-static void
-swiz_write_1(struct alpha_busspace *space, size_t offset, u_int8_t data)
-{
-	struct swiz_space *swiz = (struct swiz_space *) space;
-	if (swiz->sethae)
-		offset = swiz->sethae(swiz->arg, offset);
-	SPARSE_WRITE_BYTE(swiz->base, offset, data);
-	alpha_mb();
-}
-
-static void
-swiz_write_2(struct alpha_busspace *space, size_t offset, u_int16_t data)
-{
-	struct swiz_space *swiz = (struct swiz_space *) space;
-	if (swiz->sethae)
-		offset = swiz->sethae(swiz->arg, offset);
-	SPARSE_WRITE_WORD(swiz->base, offset, data);
-	alpha_mb();
-}
-
-static void
-swiz_write_4(struct alpha_busspace *space, size_t offset, u_int32_t data)
-{
-	struct swiz_space *swiz = (struct swiz_space *) space;
-	if (swiz->sethae)
-		offset = swiz->sethae(swiz->arg, offset);
-	SPARSE_WRITE_LONG(swiz->base, offset, data);
-	alpha_mb();
-}
-
-static struct alpha_busspace_ops swiz_space_ops = {
-	swiz_read_1,
-	swiz_read_2,
-	swiz_read_4,
-
-	busspace_generic_read_multi_1,
-	busspace_generic_read_multi_2,
-	busspace_generic_read_multi_4,
-
-	busspace_generic_read_region_1,
-	busspace_generic_read_region_2,
-	busspace_generic_read_region_4,
-
-	swiz_write_1,
-	swiz_write_2,
-	swiz_write_4,
-
-	busspace_generic_write_multi_1,
-	busspace_generic_write_multi_2,
-	busspace_generic_write_multi_4,
-
-	busspace_generic_write_region_1,
-	busspace_generic_write_region_2,
-	busspace_generic_write_region_4,
-
-	busspace_generic_set_multi_1,
-	busspace_generic_set_multi_2,
-	busspace_generic_set_multi_4,
-    
-	busspace_generic_set_region_1,
-	busspace_generic_set_region_2,
-	busspace_generic_set_region_4,
-    
-	busspace_generic_copy_region_1,
-	busspace_generic_copy_region_2,
-	busspace_generic_copy_region_4,
-
-	busspace_generic_barrier,
-};
-
-void
-swiz_init_space(struct swiz_space *swiz, u_int64_t base)
-{
-	swiz->ops = &swiz_space_ops;
-	swiz->base = base;
-	swiz->sethae = 0;
-	swiz->arg = 0;
-}
-
-void swiz_init_space_hae(struct swiz_space *swiz, u_int64_t base,
-			 swiz_sethae_fn sethae, void *arg)
-{
-	swiz->ops = &swiz_space_ops;
-	swiz->base = base;
-	swiz->sethae = sethae;
-	swiz->arg = arg;
-}
-
diff --git a/sys/alpha/pci/t2.c b/sys/alpha/pci/t2.c
deleted file mode 100644
index ea6be8a..0000000
--- a/sys/alpha/pci/t2.c
+++ /dev/null
@@ -1,642 +0,0 @@
-/*-
- * Copyright (c) 2000 Andrew Gallatin & Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Portions of this file were obtained from Compaq intellectual
- * property which was made available under the following copyright:
- *
- * *****************************************************************
- * *                                                               *
- * *    Copyright Compaq Computer Corporation, 2000                *
- * *                                                               *
- * *   Permission to use, copy, modify, distribute, and sell       *
- * *   this software and its documentation for any purpose is      *
- * *   hereby granted without fee, provided that the above         *
- * *   copyright notice appear in all copies and that both         *
- * *   that copyright notice and this permission notice appear     *
- * *   in supporting documentation, and that the name of           *
- * *   Compaq Computer Corporation not be used in advertising      *
- * *   or publicity pertaining to distribution of the software     *
- * *   without specific, written prior permission.  Compaq         *
- * *   makes no representations about the suitability of this      *
- * *   software for any purpose.  It is provided "AS IS"           *
- * *   without express or implied warranty.                        *
- * *                                                               *
- * *****************************************************************
- */
-
-/*
- * T2 CBUS to PCI bridge
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/malloc.h>
-#include <sys/module.h>
-#include <sys/mutex.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/proc.h>
-#include <sys/rman.h>
-#include <sys/interrupt.h>
-
-#include <dev/pci/pcivar.h>
-#include <alpha/pci/t2reg.h>
-#include <alpha/pci/t2var.h>
-#include <alpha/isa/isavar.h>
-
-#include <machine/cpuconf.h>
-#include <machine/intr.h>
-#include <machine/intrcnt.h>
-#include <machine/md_var.h>
-#include <machine/resource.h>
-#include <machine/sgmap.h>
-#include <machine/swiz.h>
-
-#include <vm/vm.h>
-#include <vm/vm_page.h>
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa + sable_lynx_base)
-
-vm_offset_t	sable_lynx_base = 0UL;
-
-volatile t2_csr_t *t2_csr[2];
-static int pci_int_type[2];
-
-static devclass_t	t2_devclass;
-static device_t		t2_0;		/* XXX only one for now */
-
-struct t2_softc {
-	int		junk;
-};
-
-#define T2_SOFTC(dev)	(struct t2_softc*) device_get_softc(dev)
-
-static alpha_chipset_read_hae_t	t2_read_hae;
-static alpha_chipset_write_hae_t t2_write_hae;
-
-static alpha_chipset_t t2_chipset = {
-	t2_read_hae,
-	t2_write_hae,
-};
-
-static u_int32_t	t2_hae_mem[2];
-
-#define REG1 (1UL << 24)
-
-static u_int32_t
-t2_set_hae_mem(void *arg, u_int32_t pa)
-{
-	register_t s; 
-	u_int32_t msb;
-	int hose;
-
-	hose = (long)arg;
-
-	if(pa >= REG1){
-		msb = pa & 0xf8000000;
-		pa -= msb;
-		msb >>= 27;	/* t2 puts high bits in the bottom of the register */
-		s = intr_disable();
-		if (msb != t2_hae_mem[hose]) {
-			t2_hae_mem[hose] = msb;
-			t2_csr[hose]->hae0_1 = t2_hae_mem[hose];
-			alpha_mb();
-			t2_hae_mem[hose] = t2_csr[hose]->hae0_1;
-		}
-		intr_restore(s);
-	}
-	return pa;
-}
-
-static u_int64_t
-t2_read_hae(void)
-{
-	return t2_hae_mem[0] << 27;
-}
-
-static void
-t2_write_hae(u_int64_t hae)
-{
-	u_int32_t pa = hae;
-	t2_set_hae_mem(0, pa);
-}
-
-static int t2_probe(device_t dev);
-static int t2_attach(device_t dev);
-static int t2_setup_intr(device_t dev, device_t child,
-			    struct resource *irq, int flags,
-			    void *intr, void *arg, void **cookiep);
-static int t2_teardown_intr(device_t dev, device_t child,
-			    struct resource *irq, void *cookie);
-static void
-t2_dispatch_intr(void *frame, unsigned long vector);
-static void
-t2_machine_check(unsigned long mces, struct trapframe *framep, 
-		 unsigned long vector, unsigned long param);
-
-
-static device_method_t t2_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,			t2_probe),
-	DEVMETHOD(device_attach,		t2_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_setup_intr,		t2_setup_intr),
-	DEVMETHOD(bus_teardown_intr,		t2_teardown_intr),
-
-	{ 0, 0 }
-};
-
-static driver_t t2_driver = {
-	"t2",
-	t2_methods,
-	sizeof(struct t2_softc),
-};
-
-
-#define T2_SGMAP_BASE		(8*1024*1024)
-#define T2_SGMAP_SIZE		(8*1024*1024)
-
-static void
-t2_sgmap_invalidate(void)
-{
-	u_int64_t val;
-
-	alpha_mb();
-	val = REGVAL64(T2_IOCSR);
-	val |= T2_IOCSRL_ITLB;
-	REGVAL64(T2_IOCSR) = val;
-	alpha_mb();
-	alpha_mb();
-	val = REGVAL64(T2_IOCSR);
-	val &= ~T2_IOCSRL_ITLB;
-	REGVAL64(T2_IOCSR) = val;
-	alpha_mb();
-	alpha_mb();
-}
-
-static void
-t2_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
-{
-	u_int64_t *sgtable = arg;
-	int index = alpha_btop(ba - T2_SGMAP_BASE);
-
-	if (pa) {
-		if (pa > (1L<<32))
-			panic("t2_sgmap_map: can't map address 0x%lx", pa);
-		sgtable[index] = ((pa >> 13) << 1) | 1;
-	} else {
-		sgtable[index] = 0;
-	}
-	alpha_mb();
-	t2_sgmap_invalidate();
-}
-
-
-static void
-t2_init_sgmap(int h)
-{
-	void *sgtable;
-
-	/*
-	 * First setup Window 2 to map 8Mb to 16Mb with an
-	 * sgmap. Allocate the map aligned to a 32 boundary.
-	 *
-	 *  bits 31..20 of WBASE represent the pci start address
-	 *  (in units of 1Mb), and bits 11..0 represent the pci
-	 *  end address
-	 */
-	t2_csr[h]->wbase2 = T2_WSIZE_8M|T2_WINDOW_ENABLE|T2_WINDOW_SG
-	                     | ((T2_SGMAP_BASE >> 20) << 20)
-	                     | ((T2_SGMAP_BASE + T2_SGMAP_SIZE) >> 20);
-	t2_csr[h]->wmask2 = T2_WMASK_8M;
-	alpha_mb();
-
-	sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
-			       0, (1L<<34),
-			       32*1024, (1L<<34));
-	if (!sgtable)
-		panic("t2_init_sgmap: can't allocate page table");
-
-	t2_csr[h]->tbase2 =
-	    (pmap_kextract((vm_offset_t) sgtable) >> T2_TBASE_SHIFT);
-
-	chipset.sgmap = sgmap_map_create(T2_SGMAP_BASE,
-					 T2_SGMAP_BASE + T2_SGMAP_SIZE,
-					 t2_sgmap_map, sgtable);
-	chipset.pci_sgmap = NULL;
-	chipset.dmsize = 2UL * 1024UL * 1024UL * 1024UL;
-	chipset.dmoffset = 1UL * 1024UL * 1024UL * 1024UL;
-}
-
-static void
-t2_csr_init(int h)
-{
-	/* 
-	 * initialize the DMA windows
-	 */
-	t2_csr[h]->wbase1 = T2_WSIZE_1G|T2_WINDOW_ENABLE|T2_WINDOW_DIRECT|0x7ff;
-	t2_csr[h]->wmask1 = T2_WMASK_1G;
-	t2_csr[h]->tbase1 = 0x0;
-
-	t2_csr[h]->wbase2 = 0x0;
-
-	/* 
-	 *  enable the PCI "Hole" for ISA devices which use memory in
-	 *  the 512k - 1MB range
-	 */
-	t2_csr[h]->hbase = 1 << 13;
-	t2_init_sgmap(0);
-
-	/* initialize the HAEs */
-	t2_csr[h]->hae0_1 = 0x0;
-	alpha_mb();
-	t2_csr[h]->hae0_2 = 0x0;
-	alpha_mb();
-	t2_csr[h]->hae0_3 = 0x0;
-	alpha_mb();
-
-}
-
-/*
- * Perform basic chipset init/fixup.  Called by various early
- * consumers to ensure that the system will work before the 
- * bus methods are invoked.
- *
- */
-
-void
-t2_init()
-{
-	static int initted = 0;
-	static struct swiz_space io_space, mem_space;
-
-	if (initted) return;
-	initted = 1;
-
-	swiz_init_space(&io_space, KV(T2_PCI_SIO));
-	swiz_init_space_hae(&mem_space, KV(T2_PCI_SPARSE),
-			    t2_set_hae_mem, 0);
-
-	busspace_isa_io = (struct alpha_busspace *) &io_space;
-	busspace_isa_mem = (struct alpha_busspace *) &mem_space;
-
-	chipset = t2_chipset;
-
-}
-
-static int
-t2_probe(device_t dev)
-{
-	int h, t2_num_hoses = 1;
-	device_t child;
-
-	if (t2_0)
-		return ENXIO;
-
-	t2_0 = dev;
-	device_set_desc(dev, "T2 Core Logic chipset"); 
-	t2_csr[0] = (t2_csr_t *)
-	    ALPHA_PHYS_TO_K0SEG(sable_lynx_base + PCI0_BASE);
-	t2_csr[1] = (t2_csr_t *)
-	    ALPHA_PHYS_TO_K0SEG(sable_lynx_base + PCI1_BASE);
-
-	/* Look at the rev of the chip.  If the high bit is set in the
-	 * rev field then we have either a T3 or a T4 chip, so use the
-	 * new interrupt structure.  If it is clear, then we have a T2
-	 * so use the old way */
-
-	platform.mcheck_handler = t2_machine_check;
-
-	if (((t2_csr[0]->iocsr) >> 35) & 1)
-		pci_int_type[0] = 1;
-	 else 
-		pci_int_type[0] = 0;
-
-	device_printf(dev, "using interrupt type %d on pci bus 0\n", 
-	    pci_int_type[0]);
-
-	if (!badaddr(__DEVOLATILE(void *, &t2_csr[1]->tlbbr), sizeof(long))) {
-		pci_int_type[1] = 1; /* PCI1 always uses the new scheme */
-		/* Clear any errors that the BADADDR probe may have caused */
-		t2_csr[1]->cerr1 |= t2_csr[1]->cerr1;
-		t2_csr[1]->pcierr1 |= t2_csr[1]->pcierr1;
-		device_printf(dev, "found EXT_IO!!!!!\n");
-		/* t2_num_hoses = 2; XXX not ready for this yet */
-	}
-
-	for (h = 0; h < t2_num_hoses; h++)
-		t2_csr_init(h);
-
-	
-	child = device_add_child(dev, "pcib", 0);
-	device_set_ivars(child, 0);
-
-	return 0;
-}
-
-static int
-t2_attach(device_t dev)
-{
-	t2_init();
-
-	set_iointr(t2_dispatch_intr);
-	platform.isa_setup_intr = t2_setup_intr;
-	platform.isa_teardown_intr = t2_teardown_intr;
-
-	snprintf(chipset_type, sizeof(chipset_type), "t2");
-
-	bus_generic_attach(dev);
-
-	return 0;
-}
-
-
-/*
- * magical mystery table partly obtained from Linux
- * at least some of their values for PCI masks
- * were incorrect, and I've filled in my own extrapolations
- * XXX this needs more testers 
- */
-
-unsigned long t2_shadow_mask = -1L;
-static const char irq_to_mask[40] = {
-	-1,  6, -1,  8, 15, 12,  7,  9,		/* ISA 0-7  */
-	-1, 16, 17, 18,  3, -1, 21, 22, 	/* ISA 8-15 */
-	-1, -1, -1, -1, -1, -1, -1, -1,		/* ?? EISA XXX */
-	-1, -1, -1, -1, -1, -1, -1, -1,		/* ?? EISA XXX */
-	 0,  1,  2,  3,  4,  5,  6,  7		/* PCI 0-7 XXX */
-};
-
-
-static void
-t2_8259_disable_mask(int mask)
-{
-	t2_shadow_mask |= (1UL << mask);
-
-	if (mask <= 7)
-		outb(SLAVE0_ICU, t2_shadow_mask);
-	else if (mask <= 15)
-		outb(SLAVE1_ICU, t2_shadow_mask >> 8);
-	else 
-		outb(SLAVE2_ICU, t2_shadow_mask >> 16);
-}
-
-static void
-t2_8259_enable_mask(int mask)
-{
-	t2_shadow_mask &= ~(1UL << mask);
-
-	if (mask <= 7)
-		outb(SLAVE0_ICU, t2_shadow_mask);
-	else if (mask <= 15)
-		outb(SLAVE1_ICU, t2_shadow_mask >> 8);
-	else 
-		outb(SLAVE2_ICU, t2_shadow_mask >> 16);
-}
-
-
-static void 
-t2_eoi( int vector)
-{
-	int irq, hose;
-
-	hose = (vector >= 0xC00);
-	irq = (vector - 0x800) >> 4;
-
-	if (pci_int_type[hose]) {
-
-		/* New interrupt scheme.  Both PCI0 and PCI1 can use
-		 * the same handler.  Dispatching interrupts with the
-		 * IC IC chip is easy.  We simply write the vector
-		 * address  register (var) on the T3/T4 (offset
-		 * 0x480) with the IRQ  level (0 - 63) of what came in.  */
-		t2_csr[hose]->var = (u_long) irq;
-		alpha_mb();
-		alpha_mb();
-	} else {
-		switch (irq) {
-		case 0 ... 7:
-			outb(SLAVE0_ICU-1, (0xe0 | (irq)));
-			outb(MASTER_ICU-1, (0xe0 | 1));
-			break;
-		case 8 ... 15:
-			outb(SLAVE1_ICU-1, (0xe0 | (irq - 8)));
-			outb(MASTER_ICU-1, (0xe0 | 3));
-			break;
-		case 16 ... 24:
-			outb(SLAVE2_ICU-1, (0xe0 | (irq - 16)));
-			outb(MASTER_ICU-1, (0xe0 | 4));
-			break;
-		}	
-	}
-}
-
-static void
-t2_enable_vec(uintptr_t vector)
-{
-	int irq, hose;
-	u_long IC_mask, scratch;
-
-	hose = (vector >= 0xC00);
-	irq = (vector - 0x800) >> 4;
-
-	mtx_lock_spin(&icu_lock);
-	if (pci_int_type[hose]) {
-
-		/* Write the air register on the T3/T4 with the
-		 * address of the IC IC masks register (offset 0x40) */
-		t2_csr[hose]->air = 0x40;
-		alpha_mb();
-		scratch = t2_csr[hose]->air;	
-		alpha_mb();
-		IC_mask = t2_csr[hose]->dir;
-		IC_mask &= ~(1L << ( (u_long) irq));
-		t2_csr[hose]->dir = IC_mask;	
-		alpha_mb();
-		alpha_mb();
-		/*
-		 * EOI the interrupt we just enabled.
-		 */
-		t2_eoi(vector);
-	} else {
-		/* Old style 8259 (Gack!!!) interrupts */
-		t2_8259_enable_mask(irq);
-	}
-	mtx_unlock_spin(&icu_lock);
-}
-
-static void
-t2_disable_vec(uintptr_t vector)
-{
-	int hose, irq;
-	u_long scratch, IC_mask;
-
-	hose = (vector >= 0xC00);
-	irq =  (vector - 0x800) >> 4;
-
-	mtx_lock_spin(&icu_lock);
-	if (pci_int_type[hose]) {
-
-		/* Write the air register on the T3/T4 wioth the
-		 * address of the IC IC masks register (offset 0x40) */
-
-		t2_csr[hose]->air = 0x40;
-		alpha_mb();
-		scratch = t2_csr[hose]->air;	
-		alpha_mb();
-		/*
-		 * Read the dir register to fetch the mask data, 'or' in the
-		 * new disable bit, and write the data back.
-		 */
-		IC_mask = t2_csr[hose]->dir;
-		IC_mask |= (1L << ( (u_long) irq));
-		/* Set the disable bit */
-		t2_csr[hose]->dir = IC_mask;	
-		alpha_mb();
-		alpha_mb();
-	} else {
-		/* Old style 8259 (Gack!!!) interrupts */
-		t2_8259_disable_mask(irq);
-	}
-	mtx_unlock_spin(&icu_lock);
-}
-
-
-static int
-t2_setup_intr(device_t dev, device_t child,
-	       struct resource *irq, int flags,
-	       void *intr, void *arg, void **cookiep)
-{
-	int error, vector, stdio_irq, start;
-	const char *name;
-	device_t bus, parent;
-
-	name = device_get_nameunit(dev);
-	start = stdio_irq = rman_get_start(irq);
-	if (strncmp(name, "eisa", 4) == 0) {
-		if ((stdio_irq != 6 ) && (stdio_irq != 3 )) {
-			stdio_irq = 
-			    T2_EISA_IRQ_TO_STDIO_IRQ(stdio_irq);
-		}
-	} else if ((strncmp(name, "isa", 3)) == 0) {
-		stdio_irq = irq_to_mask[stdio_irq];
-	}
-
-	parent = dev;
-	do {
-		bus = parent;
-		parent = device_get_parent(bus);
-	} while (parent && strncmp("t2", device_get_nameunit(parent), 2));
-
-	if (parent && (device_get_unit(bus) != 0))
-		vector = STDIO_PCI1_IRQ_TO_SCB_VECTOR(stdio_irq);
-	else	
-		vector = STDIO_PCI0_IRQ_TO_SCB_VECTOR(stdio_irq);
-
-	error = rman_activate_resource(irq);
-	if (error)
-		return error;
-
-	error = alpha_setup_intr(device_get_nameunit(child ? child : dev),
-			vector, intr, arg, flags, cookiep,
-			&intrcnt[start], t2_disable_vec, t2_enable_vec);
-	    
-	if (error)
-		return error;
-
-	/* Enable interrupt */
-	t2_enable_vec(vector);
-	
-	if (bootverbose != 0) 
-		device_printf(child, 
-		    "interrupting at T2 irq %d (stdio irq %d)\n",
-		     start, stdio_irq);
-	return 0;
-}
-
-static int
-t2_teardown_intr(device_t dev, device_t child,
-	       struct resource *irq, void *cookie)
-{
-	int mask;
-	
-	mask = irq_to_mask[rman_get_start(irq)];
-
-	/* Disable interrupt */
-	
-	/* 
-	 *  XXX this is totally broken! 
-	 *  we don't have enough info to figure out where the interrupt 
-	 *  came from if hose != 0 and pci_int_type[hose] != 0
-	 *  We should probably carry around the vector someplace --
-	 *  that would be enough to figure out the hose and the stdio irq
-	 */
-
-	t2_shadow_mask |= (1UL << mask);
-
-	mtx_lock_spin(&icu_lock);
-	if (mask <= 7)
-		outb(SLAVE0_ICU, t2_shadow_mask);
-	else if (mask <= 15)
-		outb(SLAVE1_ICU, t2_shadow_mask >> 8);
-	else 
-		outb(SLAVE2_ICU, t2_shadow_mask >> 16);
-	mtx_unlock_spin(&icu_lock);
-
-	alpha_teardown_intr(cookie);
-	return rman_deactivate_resource(irq);
-}
-
-
-
-static void
-t2_dispatch_intr(void *frame, unsigned long vector)
-{
-	alpha_dispatch_intr(frame, vector);
-	mtx_lock_spin(&icu_lock);
-	t2_eoi(vector);
-	mtx_unlock_spin(&icu_lock);
-}
-
-static void
-t2_machine_check(unsigned long mces, struct trapframe *framep, 
-    unsigned long vector, unsigned long param)
-{
-	int expected;
-
-	expected = mc_expected;
-	machine_check(mces, framep, vector, param);
-	/* for some reason the alpha_pal_wrmces() doesn't clear all
-	   pending machine checks & we may take another */
-	mc_expected = expected;
-}
-
-DRIVER_MODULE(t2, root, t2_driver, t2_devclass, 0, 0);
diff --git a/sys/alpha/pci/t2_pci.c b/sys/alpha/pci/t2_pci.c
deleted file mode 100644
index 44288a0..0000000
--- a/sys/alpha/pci/t2_pci.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*-
- * Copyright (c) 2000 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPELCAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <dev/pci/pcivar.h>
-#include <machine/swiz.h>
-#include <machine/md_var.h>
-
-#include <alpha/pci/t2reg.h>
-#include <alpha/pci/t2var.h>
-#include <alpha/pci/pcibus.h>
-
-#include "alphapci_if.h"
-#include "pcib_if.h"
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG((pa) + sable_lynx_base)
-
-static devclass_t	pcib_devclass;
-
-static int
-t2_pcib_probe(device_t dev)
-{
-	device_t child;
-
-	device_set_desc(dev, "T2 PCI host bus adapter");
-
-	pci_init_resources();
-
-	child = device_add_child(dev, "pci", 0);
-	device_set_ivars(child, 0);
-
-	return 0;
-}
-
-static int
-t2_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
-{
-	if (which == PCIB_IVAR_BUS) {
-		*result = 0;
-		return 0;
-	}
-	return ENOENT;
-}
-
-static void *
-t2_pcib_cvt_dense(device_t dev, vm_offset_t addr)
-{
-	addr &= 0xffffffffUL;
-	return (void *) KV(addr | T2_PCI_DENSE);
-}
-
-static int
-t2_pcib_maxslots(device_t dev)
-{
-	return 9;
-}
-
-#define T2_CFGOFF(b, s, f, r)					\
-	((b) ? (((b) << 16) | ((s) << 11) | ((f) << 8) | (r))	\
-	 : ((1 << ((s) + 11)) | ((f) << 8) | (r)))
-
-#define T2_TYPE1_SETUP(b,s,old_hae3) if((b)) {			\
-        do {							\
-		(s) = intr_disable();				\
-		(old_hae3) = REGVAL(T2_HAE0_3);			\
-		alpha_mb();					\
-		REGVAL(T2_HAE0_3) = (old_hae3) | (1<<30);	\
-		alpha_mb();					\
-        } while(0);						\
-}
-
-#define T2_TYPE1_TEARDOWN(b,s,old_hae3) if((b)) {	\
-        do {						\
-		alpha_mb();				\
-		REGVAL(T2_HAE0_3) = (old_hae3);		\
-		alpha_mb();				\
-		intr_restore((s));			\
-        } while(0);					\
-}
-
-#define SWIZ_CFGREAD(b, s, f, r, width, type) do {			 \
-	type val = ~0;							 \
-	register_t ipl = 0;						 \
-	u_int32_t old_hae3 = 0;						 \
-	vm_offset_t off = T2_CFGOFF(b, s, f, r);			 \
-	vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(T2_PCI_CONF), off); \
-	alpha_mb();							 \
-	T2_TYPE1_SETUP(b,ipl,old_hae3);					 \
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			 \
-		val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv));	 \
-	}								 \
-        T2_TYPE1_TEARDOWN(b,ipl,old_hae3);				 \
-	return val;							 \
-} while (0)
-
-#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) do {		 \
-	register_t ipl = 0;							 \
-	u_int32_t old_hae3 = 0;						 \
-	vm_offset_t off = T2_CFGOFF(b, s, f, r);			 \
-	vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(T2_PCI_CONF), off); \
-	alpha_mb();							 \
-	T2_TYPE1_SETUP(b,ipl,old_hae3);					 \
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			 \
-                SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data));	 \
-		alpha_wmb();						 \
-	}								 \
-        T2_TYPE1_TEARDOWN(b,ipl,old_hae3);				 \
-	return;								 \
-} while (0)
-
-static u_int32_t
-t2_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
-		    u_int reg, int width)
-{
-	switch (width) {
-	case 1:
-		SWIZ_CFGREAD(b, s, f, reg, BYTE, u_int8_t);
-		break;
-	case 2:
-		SWIZ_CFGREAD(b, s, f, reg, WORD, u_int16_t);
-		break;
-	case 4:
-		SWIZ_CFGREAD(b, s, f, reg, LONG, u_int32_t);
-	}
-	return ~0;
-}
-
-static void
-t2_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
-		     u_int reg, u_int32_t val, int width)
-{
-	switch (width) {
-	case 1:
-		SWIZ_CFGWRITE(b, s, f, reg, val, BYTE, u_int8_t);
-		break;
-	case 2:
-		SWIZ_CFGWRITE(b, s, f, reg, val, WORD, u_int16_t);
-		break;
-	case 4:
-		SWIZ_CFGWRITE(b, s, f, reg, val, LONG, u_int32_t);
-	}
-}
-
-static device_method_t t2_pcib_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		t2_pcib_probe),
-	DEVMETHOD(device_attach,	bus_generic_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_read_ivar,	t2_pcib_read_ivar),
-	DEVMETHOD(bus_alloc_resource,	alpha_pci_alloc_resource),
-	DEVMETHOD(bus_release_resource,	pci_release_resource),
-	DEVMETHOD(bus_activate_resource, pci_activate_resource),
-	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
-	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
-
-	/* alphapci interface */
-	DEVMETHOD(alphapci_cvt_dense,	t2_pcib_cvt_dense),
-
-	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,	t2_pcib_maxslots),
-	DEVMETHOD(pcib_read_config,	t2_pcib_read_config),
-	DEVMETHOD(pcib_write_config,	t2_pcib_write_config),
-	DEVMETHOD(pcib_route_interrupt,	alpha_pci_route_interrupt),
-
-	{ 0, 0 }
-};
-
-static driver_t t2_pcib_driver = {
-	"pcib",
-	t2_pcib_methods,
-	1,
-};
-
-DRIVER_MODULE(pcib, t2, t2_pcib_driver, pcib_devclass, 0, 0);
diff --git a/sys/alpha/pci/t2reg.h b/sys/alpha/pci/t2reg.h
deleted file mode 100644
index b805201..0000000
--- a/sys/alpha/pci/t2reg.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*-
- * Copyright (c) 2000 Doug Rabson & Andrew Gallatin 
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Portions of this file were obtained from Compaq intellectual
- * property which was made available under the following copyright:
- *
- * *****************************************************************
- * *                                                               *
- * *    Copyright Compaq Computer Corporation, 2000                *
- * *                                                               *
- * *   Permission to use, copy, modify, distribute, and sell       *
- * *   this software and its documentation for any purpose is      *
- * *   hereby granted without fee, provided that the above         *
- * *   copyright notice appear in all copies and that both         *
- * *   that copyright notice and this permission notice appear     *
- * *   in supporting documentation, and that the name of           *
- * *   Compaq Computer Corporation not be used in advertising      *
- * *   or publicity pertaining to distribution of the software     *
- * *   without specific, written prior permission.  Compaq         *
- * *   makes no representations about the suitability of this      *
- * *   software for any purpose.  It is provided "AS IS"           *
- * *   without express or implied warranty.                        *
- * *                                                               *
- * *****************************************************************
- *
- * $FreeBSD$
- */
-
-
-
-/*
- * Registers in the T2 CBUS-to-PCI bridge as used in the SABLE
- * systems.
- */
-
-#define REGVAL(r)	(*(volatile int32_t *)				\
-				ALPHA_PHYS_TO_K0SEG(r + sable_lynx_base)) 
-#define REGVAL64(r)	(*(volatile int64_t *)				\
-				ALPHA_PHYS_TO_K0SEG(r + sable_lynx_base))
-
-#define SABLE_BASE	0x0UL		/* offset of SABLE CSRs */
-#define LYNX_BASE	0x8000000000UL	/* offset of LYNX CSRs */
-#define PCI0_BASE	0x38e000000UL
-#define PCI1_BASE	0x38f000000UL
-
-#define CBUS_BASE	0x380000000	/* CBUS CSRs */
-#define T2_PCI_SIO	0x3a0000000	/* PCI sparse I/O space */
-#define T2_PCI_CONF	0x390000000	/* PCI configuration space */
-#define T2_PCI_SPARSE	0x200000000	/* PCI sparse memory space */
-#define T2_PCI_DENSE	0x3c0000000	/* PCI dense memory space */
-
-#define T2_IOCSR	(CBUS_BASE + 0xe000000)
-					/* Low word */
-#define	 T2_IOCSRL_EL		0x00000002UL	/* loopback enable */
-#define	 T2_IOCSRL_ESMV		0x00000004UL	/* enable state machine visibility */
-#define	 T2_IOCSRL_PDBP		0x00000008UL	/* PCI drive bad parity */
-#define	 T2_IOCSRL_SLOT0	0x00000030UL	/* PCI slot 0 present bits */
-#define	 T2_IOCSRL_PINT		0x00000040UL	/* PCI interrupt */
-#define	 T2_IOCSRL_ENTLBEC	0x00000080UL	/* enable TLB error check */
-#define	 T2_IOCSRL_ENCCDMA	0x00000100UL	/* enable CXACK for DMA */
-#define	 T2_IOCSRL_ENXXCHG	0x00000400UL	/* enable exclusive exchange for EV5 */
-#define	 T2_IOCSRL_CAWWP0	0x00001000UL	/* CBUS command/address write wrong parity 0 */
-#define	 T2_IOCSRL_CAWWP2	0x00002000UL	/* CBUS command/address write wrong parity 2 */
-#define	 T2_IOCSRL_CDWWPE	0x00004000UL	/* CBUS data write wrong parity even */
-#define	 T2_IOCSRL_SLOT2	0x00008000UL	/* PCI slot 2 present bit */
-#define	 T2_IOCSRL_PSERR	0x00010000UL	/* power supply error */
-#define	 T2_IOCSRL_MBA7		0x00020000UL	/* MBA7 asserted */
-#define	 T2_IOCSRL_SLOT1	0x000c0000UL	/* PCI slot 1 present bits */
-#define	 T2_IOCSRL_PDWWP1	0x00100000UL	/* PCI DMA write wrong parity HW1 */
-#define	 T2_IOCSRL_PDWWP0	0x00200000UL	/* PCI DMA write wrong parity HW0 */
-#define	 T2_IOCSRL_PBR		0x00400000UL	/* PCI bus reset */
-#define	 T2_IOCSRL_PIR		0x00800000UL	/* PCI interface reset */
-#define	 T2_IOCSRL_ENCOI	0x01000000UL	/* enable NOACK, CUCERR and out-of-sync int */
-#define	 T2_IOCSRL_EPMS		0x02000000UL	/* enable PCI memory space */
-#define	 T2_IOCSRL_ETLB		0x04000000UL	/* enable TLB */
-#define	 T2_IOCSRL_EACC		0x08000000UL	/* enable atomic CBUS cycles */
-#define	 T2_IOCSRL_ITLB		0x10000000UL	/* flush TLB */
-#define	 T2_IOCSRL_ECPC		0x20000000UL	/* enable CBUS parity check */
-#define	 T2_IOCSRL_CIR		0x40000000UL	/* CBUS interface reset */
-#define	 T2_IOCSRL_EPL		0x80000000UL	/* enable PCI lock */
-					/* High word */
-#define	 T2_IOCSRH_CBBCE	0x00000001UL	/* CBUS back-to-back cycle enable */
-#define	 T2_IOCSRH_TM		0x0000000eUL	/* T2 revision number */
-#define	 T2_IOCSRH_SMVL		0x00000070UL	/* state machine visibility select */
-#define	 T2_IOCSRH_SLOT2	0x00000080UL	/* PCI slot 2 present bit */
-#define	 T2_IOCSRH_EPR		0x00000100UL	/* enable passive release */
-#define	 T2_IOCSRH_CAWWP1	0x00001000UL	/* cbus command/address write wrong parity 1 */
-#define	 T2_IOCSRH_CAWWP3	0x00002000UL	/* cbus command/address write wrong parity 3 */
-#define	 T2_IOCSRH_DWWPO	0x00004000UL	/* CBUS data write wrong parity odd */
-#define	 T2_IOCSRH_PRM		0x00100000UL	/* PCI read multiple */
-#define	 T2_IOCSRH_PWM		0x00200000UL	/* PCI write multiple */
-#define	 T2_IOCSRH_FPRDPED	0x00400000UL	/* force PCI RDPE detect */
-#define	 T2_IOCSRH_PFAPED	0x00800000UL	/* force PCI APE detect */
-#define	 T2_IOCSRH_FPWDPED	0x01000000UL	/* force PCI WDPE detect */
-#define	 T2_IOCSRH_EPNMI	0x02000000UL	/* enable PCI NMI */
-#define	 T2_IOCSRH_EPDTI	0x04000000UL	/* enable PCI DTI */
-#define	 T2_IOCSRH_EPSEI	0x08000000UL	/* enable PCI SERR interrupt */
-#define	 T2_IOCSRH_EPPEI	0x10000000UL	/* enable PCI PERR interrupt */
-#define	 T2_IOCSRH_ERDPC	0x20000000UL	/* enable PCI RDP interrupt */
-#define	 T2_IOCSRH_EADPC	0x40000000UL	/* enable PCI AP interrupt */
-#define	 T2_IOCSRH_EWDPC	0x80000000UL	/* enable PCI WDP interrupt */
-
-#define T2_CERR1	(CBUS_BASE + 0xe000020)
-#define T2_CERR2	(CBUS_BASE + 0xe000040)
-#define T2_CERR3	(CBUS_BASE + 0xe000060)
-#define T2_PERR1	(CBUS_BASE + 0xe000080)
-#define	 T2_PERR1_PWDPE		0x00000001	/* PCI write data parity error */
-#define	 T2_PERR1_PAPE		0x00000002	/* PCI address parity error */
-#define	 T2_PERR1_PRDPE		0x00000004	/* PCI read data parity error */
-#define	 T2_PERR1_PPE		0x00000008	/* PCI parity error */
-#define	 T2_PERR1_PSE		0x00000010	/* PCI system error */
-#define	 T2_PERR1_PDTE		0x00000020	/* PCI device timeout error */
-#define	 T2_PERR1_NMI		0x00000040	/* PCI NMI */
-
-#define T2_PERR2	(CBUS_BASE + 0xe0000a0)
-#define T2_PSCR		(CBUS_BASE + 0xe0000c0)
-#define T2_HAE0_1	(CBUS_BASE + 0xe0000e0)
-#define T2_HAE0_2	(CBUS_BASE + 0xe000100)
-#define T2_HBASE	(CBUS_BASE + 0xe000120)
-#define T2_WBASE1	(CBUS_BASE + 0xe000140)
-#define T2_WMASK1	(CBUS_BASE + 0xe000160)
-#define T2_TBASE1	(CBUS_BASE + 0xe000180)
-#define T2_WBASE2	(CBUS_BASE + 0xe0001a0)
-#define T2_WMASK2	(CBUS_BASE + 0xe0001c0)
-#define T2_TBASE2	(CBUS_BASE + 0xe0001e0)
-#define T2_TLBBR	(CBUS_BASE + 0xe000200)
-#define T2_HAE0_3	(CBUS_BASE + 0xe000240)
-#define T2_HAE0_4	(CBUS_BASE + 0xe000280)
-
-/*
- * DMA window constants, section 5.2.1.1.1 of the 
- * Sable I/O Specification
- */
- 
-#define T2_WINDOW_ENABLE	0x00080000
-#define T2_WINDOW_DISABLE	0x00000000
-#define T2_WINDOW_SG		0x00040000
-#define T2_WINDOW_DIRECT	0x00000000
-
-#define T2_WMASK_2G		0x7ff00000
-#define T2_WMASK_1G		0x3ff00000
-#define T2_WMASK_512M		0x1ff00000
-#define T2_WMASK_256M		0x0ff00000
-#define T2_WMASK_128M		0x07f00000
-#define T2_WMASK_64M		0x03f00000
-#define T2_WMASK_32M		0x01f00000
-#define T2_WMASK_16M		0x00f00000
-#define T2_WMASK_8M		0x00700000
-#define T2_WMASK_4M		0x00300000
-#define T2_WMASK_2M		0x00100000
-#define T2_WMASK_1M		0x00000000
-
-
-#define T2_WSIZE_2G		0x80000000
-#define T2_WSIZE_1G		0x40000000
-#define T2_WSIZE_512M		0x20000000
-#define T2_WSIZE_256M		0x10000000
-#define T2_WSIZE_128M		0x08000000
-#define T2_WSIZE_64M		0x04000000
-#define T2_WSIZE_32M		0x02000000
-#define T2_WSIZE_16M		0x01000000
-#define T2_WSIZE_8M		0x00800000
-#define T2_WSIZE_4M		0x00400000
-#define T2_WSIZE_2M		0x00200000
-#define T2_WSIZE_1M		0x00100000
-#define T2_WSIZE_0M		0x00000000
-
-#define T2_TBASE_SHIFT		1
-
-#define	MASTER_ICU	0x535
-#define	SLAVE0_ICU	0x537
-#define	SLAVE1_ICU	0x53b
-#define	SLAVE2_ICU	0x53d
-#define	SLAVE3_ICU	0x53f
-
-
-#define T2_EISA_IRQ_TO_STDIO_IRQ( x )	((x) + 7)
-#define T2_STDIO_IRQ_TO_EISA_IRQ( x )	((x) - 7)
-#define STDIO_PCI0_IRQ_TO_SCB_VECTOR( x )	(( ( x ) * 0x10) + 0x800)
-#define STDIO_PCI1_IRQ_TO_SCB_VECTOR( x )	(( ( x ) * 0x10) + 0xC00)
-
-/*
- * T4  Control and Status Registers
- *
- * All CBUS CSRs in the Cbus2 IO subsystems are in the T4 gate array.  The
- * CBUS CSRs in the T4 are all aligned on hexaword boundaries and have 
- * quadword length.  Note, this structure also works for T2 as the T2
- * registers are a proper subset of the T3/T4's.  Just make sure
- * that T2 code does not reference T3/T4-only registers.
- *
- */
-
-typedef struct {
-	u_long iocsr;	u_long fill_00[3]; /* I/O Control/Status */
-	u_long cerr1;	u_long fill_01[3]; /* Cbus Error Register 1 */
-	u_long cerr2;	u_long fill_02[3]; /* Cbus Error Register 2 */
-	u_long cerr3;	u_long fill_03[3]; /* Cbus Error Register 3 */
-	u_long pcierr1;	u_long fill_04[3]; /* PCI Error Register 1 */
-	u_long pcierr2;	u_long fill_05[3]; /* PCI Error Register 2 */
-	u_long pciscr;	u_long fill_06[3]; /* PCI Special Cycle  */
-	u_long hae0_1;	u_long fill_07[3]; /* High Address Extension 1 */
-	u_long hae0_2;	u_long fill_08[3]; /* High Address Extension 2 */
-	u_long hbase;	u_long fill_09[3]; /* PCI Hole Base */
-	u_long wbase1;	u_long fill_0a[3]; /* Window Base 1 */
-	u_long wmask1;	u_long fill_0b[3]; /* Window Mask 1 */
-	u_long tbase1;	u_long fill_0c[3]; /* Translated Base 1 */
-	u_long wbase2;	u_long fill_0d[3]; /* Window Base 2 */
-	u_long wmask2;	u_long fill_0e[3]; /* Window Mask 2 */
-	u_long tbase2;	u_long fill_0f[3]; /* Translated Base 2 */
-	u_long tlbbr;	u_long fill_10[3]; /* TLB by-pass */
-	u_long ivr;	u_long fill_11[3]; /* IVR Passive Rels/Intr Addr  (reserved on T3/T4) */
-	u_long hae0_3;	u_long fill_12[3]; /* High Address Extension 3 */
-	u_long hae0_4;	u_long fill_13[3]; /* High Address Extension 4 */
-	u_long wbase3;	u_long fill_14[3]; /* Window Base 3 */
-	u_long wmask3;	u_long fill_15[3]; /* Window Mask 3 */
-	u_long tbase3;	u_long fill_16[3]; /* Translated Base 3 */
-
-	u_long rsvd1;	u_long fill_16a[3]; /* unused location */
-
-	u_long tdr0;	u_long fill_17[3]; /* tlb data register 0 */
-	u_long tdr1;	u_long fill_18[3]; /* tlb data register 1 */
-	u_long tdr2;	u_long fill_19[3]; /* tlb data register 2 */
-	u_long tdr3;	u_long fill_1a[3]; /* tlb data register 3 */
-	u_long tdr4;	u_long fill_1b[3]; /* tlb data register 4 */
-	u_long tdr5;	u_long fill_1c[3]; /* tlb data register 5 */
-	u_long tdr6;	u_long fill_1d[3]; /* tlb data register 6 */
-	u_long tdr7;	u_long fill_1e[3]; /* tlb data register 7 */
-	u_long wbase4;	u_long fill_1f[3]; /* Window Base 4 */
-	u_long wmask4;	u_long fill_20[3]; /* Window Mask 4 */
-	u_long tbase4;	u_long fill_21[3]; /* Translated Base 4 */
-/*
- * The following 4 registers are used to get to the ICIC chip
- */
-	u_long air;	u_long fill_22[3]; /* Address Indirection register */
-	u_long var;	u_long fill_23[3]; /* Vector access register */
-	u_long dir;	u_long fill_24[3]; /* Data Indirection register */
-	u_long ice;	u_long fill_25[3]; /* IC enable register Indirection register */
-
-} t2_csr_t;
diff --git a/sys/alpha/pci/t2var.h b/sys/alpha/pci/t2var.h
deleted file mode 100644
index 73ec13e..0000000
--- a/sys/alpha/pci/t2var.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*-
- * Copyright (c) 2000 Doug Rabson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-extern vm_offset_t	sable_lynx_base;
-
-extern void t2_init(void);
diff --git a/sys/alpha/pci/tsunami.c b/sys/alpha/pci/tsunami.c
deleted file mode 100644
index d09bfcb..0000000
--- a/sys/alpha/pci/tsunami.c
+++ /dev/null
@@ -1,417 +0,0 @@
-/*-
- * Copyright (c) 1999 Andrew Gallatin
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_cpu.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/module.h>
-#include <sys/mutex.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <sys/proc.h>
-#include <sys/rman.h>
-#include <sys/interrupt.h>
-#include <sys/malloc.h>
-
-#include <dev/pci/pcivar.h>
-#include <alpha/isa/isavar.h>
-#include <alpha/pci/tsunamireg.h>
-#include <alpha/pci/tsunamivar.h>
-
-#include <machine/bwx.h>
-#include <machine/cpuconf.h>
-#include <machine/intr.h>
-#include <machine/intrcnt.h>
-#include <machine/md_var.h>
-#include <machine/resource.h>
-#include <machine/rpb.h>
-#include <machine/sgmap.h>
-
-#include <vm/vm.h>
-#include <vm/vm_page.h>
-
-#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
-
-static devclass_t	tsunami_devclass;
-static device_t		tsunami0;		/* XXX only one for now */
-
-struct tsunami_softc {
-	int		junk;		/* no softc */
-};
-
-int tsunami_num_pchips = 0;
-static volatile tsunami_pchip *pchip[2] = {pchip0, pchip1};
-
-#define TSUNAMI_SOFTC(dev)	(struct tsunami_softc*) device_get_softc(dev)
-
-static alpha_chipset_read_hae_t	tsunami_read_hae;
-static alpha_chipset_write_hae_t tsunami_write_hae;
-
-static alpha_chipset_t tsunami_chipset = {
-	tsunami_read_hae,
-	tsunami_write_hae,
-};
-
-static void tsunami_intr_enable(int);
-static void tsunami_intr_disable(int);
-
-/* 
- * There doesn't appear to be an hae on this platform
- */
-
-
-static u_int64_t
-tsunami_read_hae(void)
-{
-	return 0;  
-}
-
-static void
-tsunami_write_hae(u_int64_t hae)
-{
-}
-
-static int tsunami_probe(device_t dev);
-static int tsunami_attach(device_t dev);
-static int tsunami_setup_intr(device_t dev, device_t child, 
-			      struct resource *irq, int flags,
-			  driver_intr_t *intr, void *arg, void **cookiep);
-static int tsunami_teardown_intr(device_t dev, device_t child,
-			     struct resource *irq, void *cookie);
-
-static device_method_t tsunami_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		tsunami_probe),
-	DEVMETHOD(device_attach,	tsunami_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,      bus_generic_print_child),
-	DEVMETHOD(bus_setup_intr,	tsunami_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	tsunami_teardown_intr),
-
-	{ 0, 0 }
-};
-
-static driver_t tsunami_driver = {
-	"tsunami",
-	tsunami_methods,
-	sizeof(struct tsunami_softc),
-};
-
-static void
-pchip_init(volatile tsunami_pchip *pchip, int index)
-{
-
-	int i;
-	
-	/*
-	 * initialize the direct map DMA windows.
-	 *
-	 * leave window 0 untouched; we'll set that up for S/G DMA for 
-	 * isa devices later in the boot process
-	 *
-	 * window 1 goes at 2GB and has a length of 1 GB. It maps
-	 * physical address 0 - 1GB. The SRM console typically sets
-	 * this window up here.
-	 */
-	
-        pchip->wsba[1].reg = (2UL*1024*1024*1024) | WINDOW_ENABLE;
-        pchip->wsm[1].reg  = (1UL*1024*1024*1024 - 1) & 0xfff00000UL;
-        pchip->tba[1].reg  = 0;
-	
-	/*
-	 * window 2 goes at 3GB and has a length of 1 GB.  It maps
-	 * physical address 1GB-2GB. 
-	 */
-	
-        pchip->wsba[2].reg = (3UL*1024*1024*1024) | WINDOW_ENABLE;
-        pchip->wsm[2].reg  = (1UL*1024*1024*1024 - 1) & 0xfff00000UL;
-        pchip->tba[2].reg  = 1UL*1024*1024*1024;
-	
-	/*
-	 * window 3 is disabled.  The SRM console typically leaves it
-	 * disabled
-	 */
-	
-        pchip->wsba[3].reg = 0;
-        alpha_mb();
-	
-	if(bootverbose) {
-		printf("pchip%d:\n", index);
-		for (i = 0; i < 4; i++) {
-			printf("\twsba[%d].reg = 0x%lx\n", 
-			       i, pchip->wsba[i].reg);
-			printf("\t wsm[%d].reg = 0x%lx\n", 
-			       i, pchip->wsm[i].reg);
-			printf("\t tba[%d].reg = 0x%lx\n", 
-			       i, pchip->tba[i].reg);
-		}
-	}
-}	
-
-#define TSUNAMI_SGMAP_BASE		(8*1024*1024)
-#define TSUNAMI_SGMAP_SIZE		(8*1024*1024)
-
-static void
-tsunami_sgmap_invalidate(void)
-{
-	alpha_mb();
-	switch (tsunami_num_pchips) {
-	case 2:
-		pchip[1]->tlbia.reg = (u_int64_t)0;
-	case 1:
-		pchip[0]->tlbia.reg = (u_int64_t)0;
-	}
-	alpha_mb();
-}
-
-static void
-tsunami_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
-{
-	u_int64_t *sgtable = arg;
-	int index = alpha_btop(ba - TSUNAMI_SGMAP_BASE);
-
-	if (pa) {
-		if (pa > (1L<<32))
-			panic("tsunami_sgmap_map: can't map address 0x%lx", pa);
-		sgtable[index] = ((pa >> 13) << 1) | 1;
-	} else {
-		sgtable[index] = 0;
-	}
-	alpha_mb();
-	tsunami_sgmap_invalidate();
-}
-
-
-static void
-tsunami_init_sgmap(void)
-{
-	void *sgtable;
-	int i;
-
-	sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
-			       0, (1L<<34),
-			       32*1024, (1L<<34));
-	if (!sgtable)
-		panic("tsunami_init_sgmap: can't allocate page table");
-
-	for(i=0; i < tsunami_num_pchips; i++){
-		pchip[i]->tba[0].reg =
-			pmap_kextract((vm_offset_t) sgtable);
-		pchip[i]->wsba[0].reg |= WINDOW_ENABLE | WINDOW_SCATTER_GATHER;
-	}
-
-	chipset.sgmap = sgmap_map_create(TSUNAMI_SGMAP_BASE,
-					 TSUNAMI_SGMAP_BASE + TSUNAMI_SGMAP_SIZE,
-					 tsunami_sgmap_map, sgtable);
-	chipset.pci_sgmap = NULL;
-}
-
-void
-tsunami_init()
-{
-	static int initted = 0;
-	static struct bwx_space io_space;
-	static struct bwx_space mem_space;
-
-	if (initted) return;
-	initted = 1;
-
-	/*
-	 * Define two temporary spaces for bootstrap i/o on hose 0.
-	 */
-	bwx_init_space(&io_space, KV(TSUNAMI_IO(0)));
-	bwx_init_space(&mem_space, KV(TSUNAMI_MEM(0)));
-
-	busspace_isa_io = (struct alpha_busspace *) &io_space;
-	busspace_isa_mem = (struct alpha_busspace *) &mem_space;
-
-	chipset = tsunami_chipset;
-	platform.pci_intr_enable =  tsunami_intr_enable;
-	platform.pci_intr_disable = tsunami_intr_disable;
-	chipset.dmsize = 2UL * 1024UL * 1024UL * 1024UL;
-	chipset.dmoffset = 2UL * 1024UL * 1024UL * 1024UL;
-
-	if (platform.pci_intr_init)
-		platform.pci_intr_init();
-}
-
-static int
-tsunami_probe(device_t dev)
-{
-	device_t child;
-	int i;
-	if (tsunami0)
-		return ENXIO;
-	tsunami0 = dev;
-	device_set_desc(dev, "21271 Core Logic chipset"); 
-	if(cchip->csc.reg & CSC_P1P)
-		tsunami_num_pchips = 2;
-	else
-		tsunami_num_pchips = 1;
-
-	isa_init_intr();
-
-	for(i = 0; i < tsunami_num_pchips; i++) {
-		child = device_add_child(dev, "pcib", i);
-		pchip_init(pchip[i], i);		
-	}
-
-	return 0;
-}
-
-static int
-tsunami_attach(device_t dev)
-{
-	tsunami_init();
-
-	if (!platform.iointr)	/* XXX */
-		set_iointr(alpha_dispatch_intr);
-
-	snprintf(chipset_type, sizeof(chipset_type), "tsunami");
-	chipset_bwx = 1;
-
-	chipset_ports = TSUNAMI_IO(0);
-	chipset_memory = TSUNAMI_MEM(0);
-	chipset_dense = TSUNAMI_MEM(0);
-	bus_generic_attach(dev);
-	tsunami_init_sgmap();
-
-	return 0;
-}
-
-static void
-tsunami_disable_intr_vec(uintptr_t vector)
-{
-	int irq;
-
-	irq = (vector - 0x900) >> 4;
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_disable(irq);
-	mtx_unlock_spin(&icu_lock);
-}
-
-static void
-tsunami_enable_intr_vec(uintptr_t vector)
-{
-	int irq;
-
-	irq = (vector - 0x900) >> 4;
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_enable(irq);
-	mtx_unlock_spin(&icu_lock);
-}
-
-static int
-tsunami_setup_intr(device_t dev, device_t child,
-	       struct resource *irq, int flags,
-	       driver_intr_t *intr, void *arg, void **cookiep)
-{
-	int error, start;
-
-	error = rman_activate_resource(irq);
-	if (error)
-		return error;
-
-	start = rman_get_start(irq);
-
-	error = alpha_setup_intr(device_get_nameunit(child ? child : dev),
-			0x900 + (start << 4), intr, arg, flags, cookiep,
-			&intrcnt[INTRCNT_EB164_IRQ + start],
-			tsunami_disable_intr_vec, tsunami_enable_intr_vec);
-	if (error)
-		return error;
-
-	/* Enable PCI interrupt */
-	mtx_lock_spin(&icu_lock);
-	platform.pci_intr_enable(start);
-	mtx_unlock_spin(&icu_lock);
-
-	device_printf(child, "interrupting at TSUNAMI irq %d\n", start);
-
-	return 0;
-}
-
-static int
-tsunami_teardown_intr(device_t dev, device_t child,
-		  struct resource *irq, void *cookie)
-{
-
-	alpha_teardown_intr(cookie);
-	return rman_deactivate_resource(irq);
-
-}
-
-
-/*
- * Currently, all interrupts will be funneled through CPU 0
- */
-
-static void
-tsunami_intr_enable(int irq)
-{
-	volatile u_int64_t *mask;
-	u_int64_t saved_mask;
-
-	mask = &cchip->dim0.reg;
-	saved_mask = *mask;
-
-	saved_mask |= (1UL << (unsigned long)irq);
-	*mask = saved_mask;
-	alpha_mb();
-	alpha_mb();
-	saved_mask = *mask;
-	alpha_mb();
-	alpha_mb();
-}
-
-static void
-tsunami_intr_disable(int irq)
-{
-	volatile u_int64_t *mask;
-	u_int64_t saved_mask;
-
-	mask = &cchip->dim0.reg;
-	saved_mask = *mask;
-
-	saved_mask &= ~(1UL << (unsigned long)irq);
-	*mask = saved_mask;
-	alpha_mb();
-	saved_mask = *mask;
-	alpha_mb();
-	alpha_mb();
-}
-
-
-
-DRIVER_MODULE(tsunami, root, tsunami_driver, tsunami_devclass, 0, 0);
-
diff --git a/sys/alpha/pci/tsunami_pci.c b/sys/alpha/pci/tsunami_pci.c
deleted file mode 100644
index 9b5853c..0000000
--- a/sys/alpha/pci/tsunami_pci.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*-
- * Copyright (c) 1999 Andrew Gallatin
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/bus.h>
-#include <machine/bus.h>
-#include <machine/md_var.h>
-#include <sys/rman.h>
-#include <dev/pci/pcivar.h>
-#include <alpha/pci/tsunamireg.h>
-#include <alpha/pci/tsunamivar.h>
-#include <alpha/pci/pcibus.h>
-#include <machine/resource.h>
-#include <machine/bwx.h>
-
-#include "alphapci_if.h"
-#include "pcib_if.h"
-
-struct tsunami_hose_softc {
-	struct bwx_space io;	/* accessor for ports */
-	struct bwx_space mem;	/* accessor for memory */
-	struct rman	io_rman; /* resource manager for ports */
-	struct rman	mem_rman; /* resource manager for memory */
-};
-
-static devclass_t	pcib_devclass;
-
-
-static int
-tsunami_pcib_probe(device_t dev)
-{
-	struct tsunami_hose_softc *sc = device_get_softc(dev);
-	device_t child;
-
-	device_set_desc(dev, "21271 PCI host bus adapter");
-
-	pci_init_resources();	/* XXX probably don't need */
-	child = device_add_child(dev, "pci", -1);
-
-	bwx_init_space(&sc->io, KV(TSUNAMI_IO(device_get_unit(dev))));
-	bwx_init_space(&sc->mem, KV(TSUNAMI_MEM(device_get_unit(dev))));
-
-	sc->io_rman.rm_start = 0;
-	sc->io_rman.rm_end = ~0u;
-	sc->io_rman.rm_type = RMAN_ARRAY;
-	sc->io_rman.rm_descr = "I/O ports";
-	if (rman_init(&sc->io_rman)
-	    || rman_manage_region(&sc->io_rman, 0x0, (1L << 32)))
-		panic("tsunami_pcib_probe: io_rman");
-
-	sc->mem_rman.rm_start = 0;
-	sc->mem_rman.rm_end = ~0u;
-	sc->mem_rman.rm_type = RMAN_ARRAY;
-	sc->mem_rman.rm_descr = "I/O memory";
-	if (rman_init(&sc->mem_rman)
-	    || rman_manage_region(&sc->mem_rman, 0x0, (1L << 32)))
-		panic("tsunami_pcib_probe: mem_rman");
-
-	/*
-	 * Replace the temporary bootstrap spaces with real onys. This
-	 * isn't stictly necessary but it keeps things tidy.
-	 */
-	if (device_get_unit(dev) == 0) {
-		busspace_isa_io = (struct alpha_busspace *) &sc->io;
-		busspace_isa_mem = (struct alpha_busspace *) &sc->mem;
-	}
-
-	return 0;
-}
-
-static int
-tsunami_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
-{
-	if (which == PCIB_IVAR_BUS) {
-		*result = 0;
-	}
-	return ENOENT;
-}
-
-static void *
-tsunami_pcib_cvt_dense(device_t dev, vm_offset_t addr)
-{
-	int h = device_get_unit(dev);
-	addr &= 0xffffffffUL;
-	return (void *) KV(addr | TSUNAMI_MEM(h));
-}
-
-static void *
-tsunami_pcib_cvt_bwx(device_t dev, vm_offset_t addr)
-{
-	int h = device_get_unit(dev);
-	addr &= 0xffffffffUL;
-	return (void *) KV(addr | TSUNAMI_MEM(h));
-}
-
-static kobj_t
-tsunami_pcib_get_bustag(device_t dev, int type)
-{
-	struct tsunami_hose_softc *sc = device_get_softc(dev);
-
-	switch (type) {
-	case SYS_RES_IOPORT:
-		return (kobj_t) &sc->io;
-
-	case SYS_RES_MEMORY:
-		return (kobj_t) &sc->mem;
-	}
-
-	return 0;
-}
-
-static struct rman *
-tsunami_pcib_get_rman(device_t dev, int type)
-{
-	struct tsunami_hose_softc *sc = device_get_softc(dev);
-
-	switch (type) {
-	case SYS_RES_IOPORT:
-		return &sc->io_rman;
-
-	case SYS_RES_MEMORY:
-		return &sc->mem_rman;
-	}
-
-	return 0;
-}
-
-static int
-tsunami_pcib_maxslots(device_t dev)
-{
-	return 31;
-}
-
-static void
-tsunami_clear_abort(void)
-{
-	alpha_mb();
-	alpha_pal_draina();	
-}
-
-static int
-tsunami_check_abort(void)
-{
-/*	u_int32_t errbits;*/
-	int ba = 0;
-
-	alpha_pal_draina();	
-	alpha_mb();
-#if 0
-	errbits = REGVAL(TSUNAMI_CSR_TSUNAMI_ERR);
-	if (errbits & (TSUNAMI_ERR_RCVD_MAS_ABT|TSUNAMI_ERR_RCVD_TAR_ABT))
-		ba = 1;
-
-	if (errbits) {
-		REGVAL(TSUNAMI_CSR_TSUNAMI_ERR) = errbits;
-		alpha_mb();
-		alpha_pal_draina();
-	}
-#endif
-	return ba;
-}
-
-#define TSUNAMI_CFGADDR(b, s, f, r, h)				\
-	KV(TSUNAMI_CONF(h) | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
-
-#define CFGREAD(h, b, s, f, r, op, width, type) do {	\
-        vm_offset_t va;					\
-	type data;					\
-	va = TSUNAMI_CFGADDR(b, s, f, r, h);		\
-	tsunami_clear_abort();				\
-	if (badaddr((caddr_t)va, width)) {		\
-		tsunami_check_abort();			\
-		return ~0;				\
-	}						\
-	data = op(va);					\
-	if (tsunami_check_abort())			\
-		return ~0;				\
-	return data;					\
-} while (0)
-
-#define CFGWRITE(h, b, s, f, r, data, op, width) do {	\
-        vm_offset_t va;					\
-	va = TSUNAMI_CFGADDR(b, s, f, r, h);		\
-	tsunami_clear_abort();				\
-	if (badaddr((caddr_t)va, width))		\
-		return;					\
-	op(va, data);					\
-	tsunami_check_abort();				\
-} while (0)
-
-static u_int32_t
-tsunami_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
-			 u_int reg, int width)
-{
-	int h = device_get_unit(dev);
-	switch (width) {
-	case 1:
-		CFGREAD(h, b, s, f, reg, ldbu, 1, u_int8_t);
-		break;
-	case 2:
-		CFGREAD(h, b, s, f, reg, ldwu, 2, u_int16_t);
-		break;
-	case 4:
-		CFGREAD(h, b, s, f, reg, ldl, 4, u_int32_t);
-	}
-	return ~0;
-}
-
-static void
-tsunami_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
-			  u_int reg, u_int32_t val, int width)
-{
-	int h = device_get_unit(dev);
-	switch (width) {
-	case 1:
-		CFGWRITE(h, b, s, f, reg, val, stb, 1);
-		break;
-	case 2:
-		CFGWRITE(h, b, s, f, reg, val, stw, 2);
-		break;
-	case 4:
-		CFGWRITE(h, b, s, f, reg, val, stl, 4);
-	}
-}
-
-static device_method_t tsunami_pcib_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		tsunami_pcib_probe),
-	DEVMETHOD(device_attach,	bus_generic_attach),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_read_ivar,	tsunami_pcib_read_ivar),
-	DEVMETHOD(bus_alloc_resource,	alpha_pci_alloc_resource),
-	DEVMETHOD(bus_release_resource,	pci_release_resource),
-	DEVMETHOD(bus_activate_resource, pci_activate_resource),
-	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
-	DEVMETHOD(bus_setup_intr,	alpha_platform_pci_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	alpha_platform_pci_teardown_intr),
-
-	/* alphapci interface */
-	DEVMETHOD(alphapci_cvt_dense,	tsunami_pcib_cvt_dense),
-	DEVMETHOD(alphapci_cvt_bwx,	tsunami_pcib_cvt_bwx),
-	DEVMETHOD(alphapci_get_bustag,	tsunami_pcib_get_bustag),
-	DEVMETHOD(alphapci_get_rman,	tsunami_pcib_get_rman),
-
-	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,	tsunami_pcib_maxslots),
-	DEVMETHOD(pcib_read_config,	tsunami_pcib_read_config),
-	DEVMETHOD(pcib_write_config,	tsunami_pcib_write_config),
-	DEVMETHOD(pcib_route_interrupt,	alpha_pci_route_interrupt),
-
-	{ 0, 0 }
-};
-
-
-static driver_t tsunami_pcib_driver = {
-	"pcib",
-	tsunami_pcib_methods,
-	sizeof(struct tsunami_hose_softc),
-};
-
-
-DRIVER_MODULE(pcib, tsunami, tsunami_pcib_driver, pcib_devclass, 0, 0);
-
-
diff --git a/sys/alpha/pci/tsunamireg.h b/sys/alpha/pci/tsunamireg.h
deleted file mode 100644
index 36ecaaf..0000000
--- a/sys/alpha/pci/tsunamireg.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $FreeBSD$ */
-
-/*
- * 21271 Chipset registers and constants.
- *
- * Taken from Tsunami/Typhoon Specification Rev. 1.2
- * and Compaq Professional Workstation XP1000: Technical
- * Information, both graciously provided by Don Rice 
- */
-
-
-typedef struct {
-	volatile u_int64_t reg __aligned(64);
-} tsunami_reg;
-					/* notes */
-typedef struct { 
-	tsunami_reg	csc;		/* rw */
-	tsunami_reg	mtr;		/* rw */
-	tsunami_reg	misc;		/* rw */
-	tsunami_reg	mpd;		/* rw */
-	tsunami_reg	aar0;		/* rw */
-	tsunami_reg	aar1;		/* rw */
-	tsunami_reg	aar2;		/* rw */
-	tsunami_reg	aar3;		/* rw */
-	tsunami_reg	dim0;		/* rw */
-	tsunami_reg	dim1;		/* rw */
-	tsunami_reg	dir0;		/* ro */
-	tsunami_reg	dir1;		/* ro */
-	tsunami_reg	drir;		/* ro */
-	tsunami_reg	prben;		/* "special" */
-	tsunami_reg	iic0;		/* rw */
-	tsunami_reg	iic1;		/* rw */
-	tsunami_reg	mpr0;		/* wo */
-	tsunami_reg	mpr1;		/* wo */
-	tsunami_reg	mpr2;		/* wo */
-	tsunami_reg	mpr3;		/* wo */
-	tsunami_reg	mctl;		/* rw, Tsunami only */
-	tsunami_reg	ttr;		/* rw */
-	tsunami_reg	tdr;		/* rw */
-	tsunami_reg	dim2;		/* rw, Typhoon only */
-	tsunami_reg	dim3;		/* rw, Typhoon only */
-	tsunami_reg	dir2;		/* ro, Typhoon only */
-	tsunami_reg	dir3;		/* ro, Typhoon only */
-	tsunami_reg	iic2;		/* rw, Typhoon only */
-	tsunami_reg	iic3;		/* rw, Typhoon only */
-	tsunami_reg	pwr;		/* rw */
-} tsunami_cchip;
-
-/*
- *  cchip csc defines
- */
-#define  CSC_P1P (1L << 14)     /* pchip1 present if this bit is set in 
-				   chip->csc */
-
-typedef struct {
-	tsunami_reg	dsc;
-	tsunami_reg	str;
-	tsunami_reg	drev;
-} tsunami_dchip;
-
-typedef struct {
-	tsunami_reg	wsba[4];	/* rw */
-	tsunami_reg	wsm[4];		/* rw */
-	tsunami_reg	tba[4];		/* rw */
-	tsunami_reg	pctl;		/* rw */
-	tsunami_reg	plat;		/* ro */
-	tsunami_reg	reserved;	/* rw */
-	tsunami_reg	perror;		/* rw */
-	tsunami_reg	perrmask;	/* rw */
-	tsunami_reg	perrset;	/* wo */
-	tsunami_reg	tlbiv;		/* wo */
-	tsunami_reg	tlbia;		/* wo */
-	tsunami_reg	pmonctl;	/* rw */
-	tsunami_reg	pmoncnt;	/* rw */
-} tsunami_pchip;
-
-/*
- * pchip window defines
- */
-#define WINDOW_ENABLE           0x1
-#define WINDOW_DISABLE          0x0
-#define WINDOW_SCATTER_GATHER   0x2
-#define WINDOW_DIRECT_MAPPED    0x0
-
-
-
-#define KV(pa)          ALPHA_PHYS_TO_K0SEG(pa)
-
-#define cchip		((tsunami_cchip *)(KV(0x101A0000000UL)))
-#define dchip		((tsunami_dchip *)(KV(0x101B0000800UL)))
-#define pchip0		((tsunami_pchip *)(KV(0x10180000000UL)))
-#define pchip1		((tsunami_pchip *)(KV(0x10380000000UL)))
-
-/*
- *   memory / i/o space macros
- *
- */
-#define HOSE(h)			(((unsigned long)(h)) << 33)
-#define TSUNAMI_MEM(h)		(0x10000000000UL + HOSE(h))
-#define TSUNAMI_IACK_SC(h)	(0x101F8000000UL + HOSE(h))
-#define TSUNAMI_IO(h)		(0x101FC000000UL + HOSE(h))
-#define TSUNAMI_CONF(h)		(0x101FE000000UL + HOSE(h))
-
-
-#define TSUNAMI_MAXHOSES 4
diff --git a/sys/alpha/pci/tsunamivar.h b/sys/alpha/pci/tsunamivar.h
deleted file mode 100644
index 89cb2ab..0000000
--- a/sys/alpha/pci/tsunamivar.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*-
- * Copyright (c) 1998 Andrew Gallatin
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-extern void tsunami_init(void);
-extern int tsunami_bus_within_hose(int, int);
-extern int tsunami_hose_from_bus(int);