Modify the critical section API as follows:

- The MD functions critical_enter/exit are renamed to start with a cpu_
  prefix.
- MI wrapper functions critical_enter/exit maintain a per-thread nesting
  count and a per-thread critical section saved state set when entering
  a critical section while at nesting level 0 and restored when exiting
  to nesting level 0.  This moves the saved state out of spin mutexes so
  that interlocking spin mutexes works properly.
- Most low-level MD code that used critical_enter/exit now use
  cpu_critical_enter/exit.  MI code such as device drivers and spin
  mutexes use the MI wrappers.  Note that since the MI wrappers store
  the state in the current thread, they do not have any return values or
  arguments.
- mtx_intr_enable() is replaced with a constant CRITICAL_FORK which is
  assigned to curthread->td_savecrit during fork_exit().

Tested on:	i386, alpha

3 files changed, 8 insertions, 8 deletions

diff --git a/sys/alpha/pci/cia.c b/sys/alpha/pci/cia.c
index c2bcafc..09436e3 100644
--- a/sys/alpha/pci/cia.c
+++ b/sys/alpha/pci/cia.c
@@ -156,12 +156,12 @@ cia_swiz_set_hae_mem(void *arg, u_int32_t pa)
 		u_int32_t msb = pa & REG1;
 		critical_t s;
 		
-		s = critical_enter();
+		s = cpu_critical_enter();
 		cia_hae_mem = (cia_hae_mem & ~REG1) | msb;
 		REGVAL(CIA_CSR_HAE_MEM) = cia_hae_mem;
 		alpha_mb();
 		cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
-		critical_exit(s);
+		cpu_critical_exit(s);
 	}
 	return pa & ~REG1;
 }
@@ -226,7 +226,7 @@ cia_sgmap_invalidate_pyxis(void)
 	int i;
 	critical_t s;
 
-	s = critical_enter();
+	s = cpu_critical_enter();
 	
 	/*
 	 * Put the Pyxis into PCI loopback mode.
@@ -257,7 +257,7 @@ cia_sgmap_invalidate_pyxis(void)
 	REGVAL(CIA_CSR_CTRL) = ctrl;
 	alpha_mb();
 
-	critical_exit(s);
+	cpu_critical_exit(s);
 }
 
 static void
diff --git a/sys/alpha/pci/t2.c b/sys/alpha/pci/t2.c
index c8ade0c..d9d0b9d 100644
--- a/sys/alpha/pci/t2.c
+++ b/sys/alpha/pci/t2.c
@@ -118,14 +118,14 @@ t2_set_hae_mem(void *arg, u_int32_t pa)
 		msb = pa & 0xf8000000;
 		pa -= msb;
 		msb >>= 27;	/* t2 puts high bits in the bottom of the register */
-		s = critical_enter();
+		s = cpu_critical_enter();
 		if (msb != t2_hae_mem[hose]) {
 			t2_hae_mem[hose] = msb;
 			t2_csr[hose]->hae0_1 = t2_hae_mem[hose];
 			alpha_mb();
 			t2_hae_mem[hose] = t2_csr[hose]->hae0_1;
 		}
-		critical_exit(s);
+		cpu_critical_exit(s);
 	}
 	return pa;
 }
diff --git a/sys/alpha/pci/t2_pci.c b/sys/alpha/pci/t2_pci.c
index 87a3dca..b50555f 100644
--- a/sys/alpha/pci/t2_pci.c
+++ b/sys/alpha/pci/t2_pci.c
@@ -92,7 +92,7 @@ t2_pcib_maxslots(device_t dev)
 
 #define T2_TYPE1_SETUP(b,s,old_hae3) if((b)) {			\
         do {							\
-		(s) = critical_enter();				\
+		(s) = cpu_critical_enter();			\
 		(old_hae3) = REGVAL(T2_HAE0_3);			\
 		alpha_mb();					\
 		REGVAL(T2_HAE0_3) = (old_hae3) | (1<<30);	\
@@ -105,7 +105,7 @@ t2_pcib_maxslots(device_t dev)
 		alpha_mb();				\
 		REGVAL(T2_HAE0_3) = (old_hae3);		\
 		alpha_mb();				\
-		critical_exit((s));			\
+		cpu_critical_exit((s));			\
         } while(0);					\
 }