Partially re-write T2 chipset support based on Tru64 platform support

files which Compaq open-sourced (with a BSD license).

This commit adds support for proper PCI interrupt mapping and much
better support for swizzling between "standard" isa IRQs and the stdio
irqs used by the t2.  This also adds enabling/disabling/eoi support
for AlphaServer 2100A machines.  The 2100A (or lynx) interrupt
hardware is is very different (and much nicer) than the 2100.
Previously, only AS2100 and AS2000 machines worked.

This commits also lays the groundwork for supporting ExtIO modules.
These modules are essentially a second hose.  This work is left
unfinished pending testing on real hardware.  Wilko tells me that
ExtIO modules are quite rare, and may not actually exist in the wild.

Obtained from: Tru64
Tested by: wilko

1 files changed, 91 insertions, 2 deletions

diff --git a/sys/alpha/pci/t2reg.h b/sys/alpha/pci/t2reg.h
index 339c4e1..86f04e9 100644
--- a/sys/alpha/pci/t2reg.h
+++ b/sys/alpha/pci/t2reg.h
@@ -23,6 +23,28 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
+ * Portions of this file were obtained from Compaq intellectual
+ * property which was made available under the following copyright:
+ *
+ * *****************************************************************
+ * *                                                               *
+ * *    Copyright Compaq Computer Corporation, 2000                *
+ * *                                                               *
+ * *   Permission to use, copy, modify, distribute, and sell       *
+ * *   this software and its documentation for any purpose is      *
+ * *   hereby granted without fee, provided that the above         *
+ * *   copyright notice appear in all copies and that both         *
+ * *   that copyright notice and this permission notice appear     *
+ * *   in supporting documentation, and that the name of           *
+ * *   Compaq Computer Corporation not be used in advertising      *
+ * *   or publicity pertaining to distribution of the software     *
+ * *   without specific, written prior permission.  Compaq         *
+ * *   makes no representations about the suitability of this      *
+ * *   software for any purpose.  It is provided "AS IS"           *
+ * *   without express or implied warranty.                        *
+ * *                                                               *
+ * *****************************************************************
+ *
  * $FreeBSD$
  */
 
@@ -34,12 +56,14 @@
  */
 
 #define REGVAL(r)	(*(volatile int32_t *)				\
-				ALPHA_PHYS_TO_K0SEG(r + t2_csr_base)) 
+				ALPHA_PHYS_TO_K0SEG(r + sable_lynx_base)) 
 #define REGVAL64(r)	(*(volatile int64_t *)				\
-				ALPHA_PHYS_TO_K0SEG(r + t2_csr_base))
+				ALPHA_PHYS_TO_K0SEG(r + sable_lynx_base))
 
 #define SABLE_BASE	0x0UL		/* offset of SABLE CSRs */
 #define LYNX_BASE	0x8000000000UL	/* offset of LYNX CSRs */
+#define PCI0_BASE	0x38e000000UL
+#define PCI1_BASE	0x38f000000UL
 
 #define CBUS_BASE	0x380000000	/* CBUS CSRs */
 #define T2_PCI_SIO	0x3a0000000	/* PCI sparse I/O space */
@@ -170,3 +194,68 @@
 #define	SLAVE1_ICU	0x53b
 #define	SLAVE2_ICU	0x53d
 #define	SLAVE3_ICU	0x53f
+
+
+#define T2_EISA_IRQ_TO_STDIO_IRQ( x )	((x) + 7)
+#define T2_STDIO_IRQ_TO_EISA_IRQ( x )	((x) - 7)
+#define STDIO_PCI0_IRQ_TO_SCB_VECTOR( x )	(( ( x ) * 0x10) + 0x800)
+#define STDIO_PCI1_IRQ_TO_SCB_VECTOR( x )	(( ( x ) * 0x10) + 0xC00)
+
+/*
+ * T4  Control and Status Registers
+ *
+ * All CBUS CSRs in the Cbus2 IO subsystems are in the T4 gate array.  The
+ * CBUS CSRs in the T4 are all aligned on hexaword boundaries and have 
+ * quadword length.  Note, this structure also works for T2 as the T2
+ * registers are a proper subset of the T3/T4's.  Just make sure
+ * that T2 code does not reference T3/T4-only registers.
+ *
+ */
+
+typedef struct {
+	u_long iocsr;	u_long fill_00[3]; /* I/O Control/Status */
+	u_long cerr1;	u_long fill_01[3]; /* Cbus Error Register 1 */
+	u_long cerr2;	u_long fill_02[3]; /* Cbus Error Register 2 */
+	u_long cerr3;	u_long fill_03[3]; /* Cbus Error Register 3 */
+	u_long pcierr1;	u_long fill_04[3]; /* PCI Error Register 1 */
+	u_long pcierr2;	u_long fill_05[3]; /* PCI Error Register 2 */
+	u_long pciscr;	u_long fill_06[3]; /* PCI Special Cycle  */
+	u_long hae0_1;	u_long fill_07[3]; /* High Address Extension 1 */
+	u_long hae0_2;	u_long fill_08[3]; /* High Address Extension 2 */
+	u_long hbase;	u_long fill_09[3]; /* PCI Hole Base */
+	u_long wbase1;	u_long fill_0a[3]; /* Window Base 1 */
+	u_long wmask1;	u_long fill_0b[3]; /* Window Mask 1 */
+	u_long tbase1;	u_long fill_0c[3]; /* Translated Base 1 */
+	u_long wbase2;	u_long fill_0d[3]; /* Window Base 2 */
+	u_long wmask2;	u_long fill_0e[3]; /* Window Mask 2 */
+	u_long tbase2;	u_long fill_0f[3]; /* Translated Base 2 */
+	u_long tlbbr;	u_long fill_10[3]; /* TLB by-pass */
+	u_long ivr;	u_long fill_11[3]; /* IVR Passive Rels/Intr Addr  (reserved on T3/T4) */
+	u_long hae0_3;	u_long fill_12[3]; /* High Address Extension 3 */
+	u_long hae0_4;	u_long fill_13[3]; /* High Address Extension 4 */
+	u_long wbase3;	u_long fill_14[3]; /* Window Base 3 */
+	u_long wmask3;	u_long fill_15[3]; /* Window Mask 3 */
+	u_long tbase3;	u_long fill_16[3]; /* Translated Base 3 */
+
+	u_long rsvd1;	u_long fill_16a[3]; /* unused location */
+
+	u_long tdr0;	u_long fill_17[3]; /* tlb data register 0 */
+	u_long tdr1;	u_long fill_18[3]; /* tlb data register 1 */
+	u_long tdr2;	u_long fill_19[3]; /* tlb data register 2 */
+	u_long tdr3;	u_long fill_1a[3]; /* tlb data register 3 */
+	u_long tdr4;	u_long fill_1b[3]; /* tlb data register 4 */
+	u_long tdr5;	u_long fill_1c[3]; /* tlb data register 5 */
+	u_long tdr6;	u_long fill_1d[3]; /* tlb data register 6 */
+	u_long tdr7;	u_long fill_1e[3]; /* tlb data register 7 */
+	u_long wbase4;	u_long fill_1f[3]; /* Window Base 4 */
+	u_long wmask4;	u_long fill_20[3]; /* Window Mask 4 */
+	u_long tbase4;	u_long fill_21[3]; /* Translated Base 4 */
+/*
+ * The following 4 registers are used to get to the ICIC chip
+ */
+	u_long air;	u_long fill_22[3]; /* Address Indirection register */
+	u_long var;	u_long fill_23[3]; /* Vector access register */
+	u_long dir;	u_long fill_24[3]; /* Data Indirection register */
+	u_long ice;	u_long fill_25[3]; /* IC enable register Indirection register */
+
+} t2_csr_t;