* Completely rewrite the alpha busspace to hide the implementation from

  the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
  which call busspace.
* Rework pci config accesses to route through the pcib device instead of
  calling a MD function directly.

With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.

1 files changed, 16 insertions, 309 deletions

diff --git a/sys/alpha/pci/apecs.c b/sys/alpha/pci/apecs.c
index d23df8a..e15aee1 100644
--- a/sys/alpha/pci/apecs.c
+++ b/sys/alpha/pci/apecs.c
@@ -94,105 +94,14 @@ struct apecs_softc {
 
 #define APECS_SOFTC(dev)	(struct apecs_softc*) device_get_softc(dev)
 
-static alpha_chipset_inb_t	apecs_swiz_inb;
-static alpha_chipset_inw_t	apecs_swiz_inw;
-static alpha_chipset_inl_t	apecs_swiz_inl;
-static alpha_chipset_outb_t	apecs_swiz_outb;
-static alpha_chipset_outw_t	apecs_swiz_outw;
-static alpha_chipset_outl_t	apecs_swiz_outl;
-static alpha_chipset_readb_t	apecs_swiz_readb;
-static alpha_chipset_readw_t	apecs_swiz_readw;
-static alpha_chipset_readl_t	apecs_swiz_readl;
-static alpha_chipset_writeb_t	apecs_swiz_writeb;
-static alpha_chipset_writew_t	apecs_swiz_writew;
-static alpha_chipset_writel_t	apecs_swiz_writel;
-static alpha_chipset_maxdevs_t	apecs_swiz_maxdevs;
-static alpha_chipset_cfgreadb_t	apecs_swiz_cfgreadb;
-static alpha_chipset_cfgreadw_t	apecs_swiz_cfgreadw;
-static alpha_chipset_cfgreadl_t	apecs_swiz_cfgreadl;
-static alpha_chipset_cfgwriteb_t  apecs_swiz_cfgwriteb;
-static alpha_chipset_cfgwritew_t  apecs_swiz_cfgwritew;
-static alpha_chipset_cfgwritel_t  apecs_swiz_cfgwritel;
-static alpha_chipset_addrcvt_t    apecs_cvt_dense;
 static alpha_chipset_read_hae_t	apecs_read_hae;
 static alpha_chipset_write_hae_t apecs_write_hae;
 
 static alpha_chipset_t apecs_swiz_chipset = {
-	apecs_swiz_inb,
-	apecs_swiz_inw,
-	apecs_swiz_inl,
-	apecs_swiz_outb,
-	apecs_swiz_outw,
-	apecs_swiz_outl,
-	apecs_swiz_readb,
-	apecs_swiz_readw,
-	apecs_swiz_readl,
-	apecs_swiz_writeb,
-	apecs_swiz_writew,
-	apecs_swiz_writel,
-	apecs_swiz_maxdevs,
-	apecs_swiz_cfgreadb,
-	apecs_swiz_cfgreadw,
-	apecs_swiz_cfgreadl,
-	apecs_swiz_cfgwriteb,
-	apecs_swiz_cfgwritew,
-	apecs_swiz_cfgwritel,
-	apecs_cvt_dense,
-	NULL,
 	apecs_read_hae,
 	apecs_write_hae,
 };
 
-static int
-apecs_swiz_maxdevs(u_int b)
-{
-	return 12;		/* XXX */
-}
-
-
-
-static u_int8_t
-apecs_swiz_inb(u_int32_t port)
-{
-	alpha_mb();
-	return SPARSE_READ_BYTE(KV(APECS_PCI_SIO), port);
-}
-
-static u_int16_t
-apecs_swiz_inw(u_int32_t port)
-{
-	alpha_mb();
-	return SPARSE_READ_WORD(KV(APECS_PCI_SIO), port);
-}
-
-static u_int32_t
-apecs_swiz_inl(u_int32_t port)
-{
-	alpha_mb();
-	return SPARSE_READ_LONG(KV(APECS_PCI_SIO), port);
-}
-
-static void
-apecs_swiz_outb(u_int32_t port, u_int8_t data)
-{
-	SPARSE_WRITE_BYTE(KV(APECS_PCI_SIO), port, data);
-	alpha_wmb();
-}
-
-static void
-apecs_swiz_outw(u_int32_t port, u_int16_t data)
-{
-	SPARSE_WRITE_WORD(KV(APECS_PCI_SIO), port, data);
-	alpha_wmb();
-}
-
-static void
-apecs_swiz_outl(u_int32_t port, u_int32_t data)
-{
-	SPARSE_WRITE_LONG(KV(APECS_PCI_SIO), port, data);
-	alpha_wmb();
-}
-
 /*
  * Memory functions.
  * 
@@ -204,14 +113,14 @@ apecs_swiz_outl(u_int32_t port, u_int32_t data)
 static u_int32_t	apecs_hae_mem;
 
 #define REG1 (1UL << 24)
-static __inline  void
-apecs_swiz_set_hae_mem(u_int32_t *pa)
+static u_int32_t
+apecs_set_hae_mem(void *arg, u_int32_t pa)
 {
 	int s; 
 	u_int32_t msb;
-	if(*pa >= REG1){
-		msb = *pa & 0xf8000000;
-		*pa -= msb;
+	if (pa >= REG1){
+		msb = pa & 0xf8000000;
+		pa -= msb;
 		s = splhigh();
                 if (msb != apecs_hae_mem) {
 			apecs_hae_mem = msb;
@@ -221,217 +130,7 @@ apecs_swiz_set_hae_mem(u_int32_t *pa)
 		}
 		splx(s);
 	}
-}
-
-static u_int8_t
-apecs_swiz_readb(u_int32_t pa)
-{
-	alpha_mb();
-	apecs_swiz_set_hae_mem(&pa);
-	return SPARSE_READ_BYTE(KV(APECS_PCI_SPARSE), pa);
-}
-
-static u_int16_t
-apecs_swiz_readw(u_int32_t pa)
-{
-	alpha_mb();
-	apecs_swiz_set_hae_mem(&pa);
-	return SPARSE_READ_WORD(KV(APECS_PCI_SPARSE), pa);
-}
-
-static u_int32_t
-apecs_swiz_readl(u_int32_t pa)
-{
-	alpha_mb();
-	apecs_swiz_set_hae_mem(&pa);
-	return SPARSE_READ_LONG(KV(APECS_PCI_SPARSE), pa);
-}
-
-static void
-apecs_swiz_writeb(u_int32_t pa, u_int8_t data)
-{
-	apecs_swiz_set_hae_mem(&pa);
-	SPARSE_WRITE_BYTE(KV(APECS_PCI_SPARSE), pa, data);
-	alpha_wmb();
-}
-
-static void
-apecs_swiz_writew(u_int32_t pa, u_int16_t data)
-{
-	apecs_swiz_set_hae_mem(&pa);
-	SPARSE_WRITE_WORD(KV(APECS_PCI_SPARSE), pa, data);
-	alpha_wmb();
-}
-
-
-static void
-apecs_swiz_writel(u_int32_t pa, u_int32_t data)
-{
-	apecs_swiz_set_hae_mem(&pa);
-	SPARSE_WRITE_LONG(KV(APECS_PCI_SPARSE), pa, data);
-	alpha_wmb();
-
-}
-
-
-#define APECS_SWIZ_CFGOFF(b, s, f, r) \
-	(((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
-
-#define APECS_TYPE1_SETUP(b,s,old_haxr2) if((b)) {		\
-        do {						\
-		(s) = splhigh();			\
-		(old_haxr2) = REGVAL(EPIC_HAXR2);	\
-		alpha_mb();				\
-		REGVAL(EPIC_HAXR2) = (old_haxr2) | 0x1;	\
-		alpha_mb();				\
-        } while(0);					\
-}
-
-#define APECS_TYPE1_TEARDOWN(b,s,old_haxr2) if((b)) {	\
-        do {						\
-		alpha_mb();				\
-		REGVAL(EPIC_HAXR2) = (old_haxr2);	\
-		alpha_mb();				\
-		splx((s));				\
-        } while(0);					\
-}
-
-#define SWIZ_CFGREAD(b, s, f, r, width, type)				\
-	type val = ~0;							\
-	int ipl = 0;							\
-	u_int32_t old_haxr2 = 0;					\
-	struct apecs_softc* sc = APECS_SOFTC(apecs0);			\
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);		\
-	vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off);	\
-	alpha_mb();							\
-	APECS_TYPE1_SETUP(b,ipl,old_haxr2);				\
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			\
-		val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv));	\
-	}								\
-        APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2);				\
-	return val;							
-
-#define SWIZ_CFGWRITE(b, s, f, r, data, width, type)			\
-	int ipl = 0;							\
-	u_int32_t old_haxr2 = 0;					\
-	struct apecs_softc* sc = APECS_SOFTC(apecs0);			\
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);		\
-	vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off);	\
-	alpha_mb();							\
-	APECS_TYPE1_SETUP(b,ipl,old_haxr2);				\
-	if (!badaddr((caddr_t)kv, sizeof(type))) {			\
-                SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data));	\
-		alpha_wmb();						\
-	}								\
-        APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2);				\
-	return;							
-
-#if 1
-static u_int8_t
-apecs_swiz_cfgreadb(u_int h, u_int b, u_int s, u_int f, u_int r)
-{
-	SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t);
-}
-
-static u_int16_t
-apecs_swiz_cfgreadw(u_int h, u_int b, u_int s, u_int f, u_int r)
-{
-	SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t);
-}
-
-static u_int32_t
-apecs_swiz_cfgreadl(u_int h, u_int b, u_int s, u_int f, u_int r)
-{
-	SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t);
-}
-
-static void
-apecs_swiz_cfgwriteb(u_int h, u_int b, u_int s, u_int f, u_int r, u_int8_t data)
-{
-	SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t);
-}
-
-static void
-apecs_swiz_cfgwritew(u_int h, u_int b, u_int s, u_int f, u_int r, u_int16_t data)
-{
-	SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t);
-}
-
-static void
-apecs_swiz_cfgwritel(u_int h, u_int b, u_int s, u_int f, u_int r, u_int32_t data)
-{
-	SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t);
-}
-
-#else
-static u_int8_t
-apecs_swiz_cfgreadb(u_int h, u_int b, u_int s, u_int f, u_int r)
-{
-	struct apecs_softc* sc = APECS_SOFTC(apecs0);
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
-	alpha_mb();
-	if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return ~0;
-	return SPARSE_READ_BYTE(sc->cfg0_base, off);
-}
-
-static u_int16_t
-apecs_swiz_cfgreadw(u_int h, u_int b, u_int s, u_int f, u_int r)
-{
-	struct apecs_softc* sc = APECS_SOFTC(apecs0);
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
-	alpha_mb();
-	if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return ~0;
-	return SPARSE_READ_WORD(sc->cfg0_base, off);
-}
-
-static u_int32_t
-apecs_swiz_cfgreadl(u_int h, u_int b, u_int s, u_int f, u_int r)
-{
-	struct apecs_softc* sc = APECS_SOFTC(apecs0);
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
-	alpha_mb();
-	if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return ~0;
-	return SPARSE_READ_LONG(sc->cfg0_base, off);
-}
-
-static void
-apecs_swiz_cfgwriteb(u_int h, u_int b, u_int s, u_int f, u_int r, u_int8_t data)
-{
-	struct apecs_softc* sc = APECS_SOFTC(apecs0);
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
-	if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return;
-	SPARSE_WRITE_BYTE(sc->cfg0_base, off, data);
-	alpha_wmb();
-}
-
-static void
-apecs_swiz_cfgwritew(u_int h, u_int b, u_int s, u_int f, u_int r, u_int16_t data)
-{
-	struct apecs_softc* sc = APECS_SOFTC(apecs0);
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
-	if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return;
-	SPARSE_WRITE_WORD(sc->cfg0_base, off, data);
-	alpha_wmb();
-}
-
-static void
-apecs_swiz_cfgwritel(u_int h, u_int b, u_int s, u_int f, u_int r, u_int32_t data)
-{
-	struct apecs_softc* sc = APECS_SOFTC(apecs0);
-	vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);
-	if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return;
-	SPARSE_WRITE_LONG(sc->cfg0_base, off, data);
-	alpha_wmb();
-}
-#endif
-
-
-static vm_offset_t
-apecs_cvt_dense(vm_offset_t addr)
-{
-	addr &= 0xffffffffUL;
-	return (addr | APECS_PCI_DENSE);
-	
+	return pa;
 }
 
 static u_int64_t
@@ -444,7 +143,7 @@ static void
 apecs_write_hae(u_int64_t hae)
 {
 	u_int32_t pa = hae;
-	apecs_swiz_set_hae_mem(&pa);
+	apecs_set_hae_mem(0, pa);
 }
 
 static int apecs_probe(device_t dev);
@@ -495,7 +194,7 @@ apecs_sgmap_invalidate(void)
 }
 
 static void
-apecs_sgmap_map(void *arg, vm_offset_t ba, vm_offset_t pa)
+apecs_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
 {
 	u_int64_t *sgtable = arg;
 	int index = alpha_btop(ba - APECS_SGMAP_BASE);
@@ -544,10 +243,18 @@ void
 apecs_init()
 {
 	static int initted = 0;
+	static struct swiz_space io_space, mem_space;
 
 	if (initted) return;
 	initted = 1;
 
+	swiz_init_space(&io_space, KV(APECS_PCI_SIO));
+	swiz_init_space_hae(&mem_space, KV(APECS_PCI_SPARSE),
+			    apecs_set_hae_mem, 0);
+
+	busspace_isa_io = (struct alpha_busspace *) &io_space;
+	busspace_isa_mem = (struct alpha_busspace *) &mem_space;
+
 	chipset = apecs_swiz_chipset;
 
 	if (platform.pci_intr_init)