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authorwkoszek <wkoszek@FreeBSD.org>2013-04-27 23:59:15 +0000
committerwkoszek <wkoszek@FreeBSD.org>2013-04-27 23:59:15 +0000
commit7016da39e36099ec2acac876a2648ac7c283145e (patch)
treeb091a3934d607912771d00fb7ac790b5532239d7 /share
parentfcb67434842e8a1a8ba60a2607b55922d35887fb (diff)
downloadFreeBSD-src-7016da39e36099ec2acac876a2648ac7c283145e.zip
FreeBSD-src-7016da39e36099ec2acac876a2648ac7c283145e.tar.gz
Polish devcfg(4) slightly: add \n after the end of every sentence.
Diffstat (limited to 'share')
-rw-r--r--share/man/man4/man4.arm/devcfg.429
1 files changed, 16 insertions, 13 deletions
diff --git a/share/man/man4/man4.arm/devcfg.4 b/share/man/man4/man4.arm/devcfg.4
index 5068fa4..392e77d 100644
--- a/share/man/man4/man4.arm/devcfg.4
+++ b/share/man/man4/man4.arm/devcfg.4
@@ -39,19 +39,20 @@ can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
.Pp
On the first write to the character device at file offset 0, the devcfg driver
asserts the top-level PL reset signals, disables the PS-PL level shifters,
-and clears the PL configuration. Write data is sent to
-the PCAP (processor configuration access port). When the PL asserts the
-DONE signal, the devcfg driver will enable the level shifters and release
-the top-level PL reset signals.
+and clears the PL configuration.
+Write data is sent to the PCAP (processor configuration access port).
+When the PL asserts the DONE signal, the devcfg driver will enable the level
+shifters and release the top-level PL reset signals.
.Pp
-The PL (FPGA) can be configured by writing the bitstream to the
-character device like this:
+The PL (FPGA) can be configured by writing the bitstream to the character
+device like this:
.Bd -literal -offset indent
cat design.bit.bin > /dev/devcfg
.Ed
.Pp
The file should not be confused with the .bit file output by the FPGA
-design tools. It is the binary form of the configuration bitstream.
+design tools.
+It is the binary form of the configuration bitstream.
The Xilinx
.Pa promgen
tool can do the conversion:
@@ -65,15 +66,17 @@ variables:
.Bl -tag -width 12
.It Va hw.fpga.pl_done
.Pp
-This variable always reflects the status of the PL's DONE signal. A 1
-means the PL section has been properly programmed.
+This variable always reflects the status of the PL's DONE signal.
+A 1 means the PL section has been properly programmed.
.It Va hw.fpga.en_level_shifters
.Pp
This variable controls if the PS-PL level shifters are enabled after the
-PL section has been reconfigured. This variable is 1 by default but setting
-it to 0 allows the PL section to be programmed with configurations that
-don't interface to the PS section of the part. Changing this value has no
-effect on the level shifters until the next device reconfiguration.
+PL section has been reconfigured.
+This variable is 1 by default but setting it to 0 allows the PL section to be
+programmed with configurations that don't interface to the PS section of the
+part.
+Changing this value has no effect on the level shifters until the next device
+reconfiguration.
.Sh FILES
/dev/devcfg Character device for
.Nm
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