bus_dma(9) cleanup.

 o Enforce TX/RX descriptor ring alignment. NS data sheet says the
   controller needs 4 bytes alignment but use 16 to cover both SiS
   and NS controllers. I don't have SiS data sheet so I'm not sure
   what is alignment restriction of SiS controller but 16 would be
   enough because it's larger than the size of a TX/RX descriptor.
   Previously sis(4) ignored the alignment restriction.
 o Enforce RX buffer alignment, 4.
   Previously sis(4) ignored RX buffer alignment restriction.
 o Limit number of TX DMA segment to be used to 16. It seems
   controller has no restriction on number of DMA segments but
   using more than 16 looks resource waste.
 o Collapse long mbuf chains with m_collapse(9) instead of calling
   expensive m_defrag(9).
 o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove
   unnecessary callbacks.
 o Initial endianness support.
 o Prefer local alignment fixup code to m_devget(9).
 o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying
   these maps in fast TX/RX path. On non-x86 architectures, this is
   very expensive operation and there is no need to do that.
 o Add missing bus_dmamap_sync(9) in TX/RX path.
 o watchdog is now unarmed only when there are no pending frames
   on controller. Previously sis(4) blindly unarmed watchdog
   without checking the number of queued frames.
 o For efficiency, loaded DMA map is reused for error frames.
 o DMA map loading failure is now gracefully handled. Previously
   sis(4) ignored any DMA map loading errors.
 o Nuke unused macros which are not appropriate for endianness
   operation.
 o Stop embedding driver maintained structures into descriptor
   rings. Because TX/RX descriptor structures are shared between
   host and controller, frequent bus_dmamap_sync(9) operations are
   required in fast path. Embedding driver structures will increase
   the size of DMA map which in turn will slow down performance.

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