diff options
author | sheldonh <sheldonh@FreeBSD.org> | 2000-03-01 14:50:24 +0000 |
---|---|---|
committer | sheldonh <sheldonh@FreeBSD.org> | 2000-03-01 14:50:24 +0000 |
commit | b45b9e3cde3c8b803fc2c4fbdb784fc378ced24d (patch) | |
tree | 0b7d3487005ae5a1da0062d675a3bf21249410eb /share/man/man4/vr.4 | |
parent | 46cac19efdca36bb719c540488e5b984e7370eca (diff) | |
download | FreeBSD-src-b45b9e3cde3c8b803fc2c4fbdb784fc378ced24d.zip FreeBSD-src-b45b9e3cde3c8b803fc2c4fbdb784fc378ced24d.tar.gz |
Remove single-space hard sentence breaks. These degrade the quality
of the typeset output, tend to make diffs harder to read and provide
bad examples for new-comers to mdoc.
Diffstat (limited to 'share/man/man4/vr.4')
-rw-r--r-- | share/man/man4/vr.4 | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/share/man/man4/vr.4 b/share/man/man4/vr.4 index 6c27b64..cf14623 100644 --- a/share/man/man4/vr.4 +++ b/share/man/man4/vr.4 @@ -45,19 +45,23 @@ The .Nm driver provides support for PCI ethernet adapters and embedded controllers based on the VIA Technologies VT3043 Rhine I and -VT86C100A Rhine II fast ethernet controller chips. This includes +VT86C100A Rhine II fast ethernet controller chips. +This includes the D-Link DFE530-TX, the Hawking Technologies PN102TX, the AOpen/Acer ALN-320, and various other commodity fast ethernet cards. .Pp The VIA Rhine chips use bus master DMA and have a descriptor layout -designed to resemble that of the DEC 21x4x "tulip" chips. The register +designed to resemble that of the DEC 21x4x "tulip" chips. +The register layout is different however and the receive filter in the Rhine chips is much simpler and is programmed through registers rather than by downloading a special setup frame through the transmit DMA engine. Transmit and receive DMA buffers must be longword -aligned. The Rhine chips are meant to be interfaced with external -physical layer devices via an MII bus. They support both +aligned. +The Rhine chips are meant to be interfaced with external +physical layer devices via an MII bus. +They support both 10 and 100Mbps speeds in either full or half duplex. .Pp The @@ -72,14 +76,16 @@ the autoselected mode by adding media options to the .Pa /etc/rc.conf file. .It 10baseT/UTP -Set 10Mbps operation. The +Set 10Mbps operation. +The .Ar mediaopt option can also be used to select either .Ar full-duplex or .Ar half-duplex modes. .It 100baseTX -Set 100Mbps (fast ethernet) operation. The +Set 100Mbps (fast ethernet) operation. +The .Ar mediaopt option can also be used to select either .Ar full-duplex @@ -119,20 +125,25 @@ The driver failed to allocate an mbuf for the transmitter ring when allocating a pad buffer or collapsing an mbuf chain into a cluster. .It "vr%d: chip is in D3 power state -- setting to D0" This message applies only to adapters which support power -management. Some operating systems place the controller in low power +management. +Some operating systems place the controller in low power mode when shutting down, and some PCI BIOSes fail to bring the chip -out of this state before configuring it. The controller loses all of +out of this state before configuring it. +The controller loses all of its PCI configuration in the D3 state, so if the BIOS does not set it back to full power mode in time, it won't be able to configure it -correctly. The driver tries to detect this condition and bring +correctly. +The driver tries to detect this condition and bring the adapter back to the D0 (full power) state, but this may not be -enough to return the driver to a fully operational condition. If +enough to return the driver to a fully operational condition. +If you see this message at boot time and the driver fails to attach the device as a network interface, you will have to perform second warm boot to have the device properly configured. .Pp Note that this condition only occurs when warm booting from another -operating system. If you power down your system prior to booting +operating system. +If you power down your system prior to booting .Fx , the card should be configured correctly. .El @@ -163,5 +174,6 @@ buffers prior to transmission in order to pacify the Rhine chips. If buffers are not aligned correctly, the chip will round the supplied buffer address and begin DMAing from the wrong location. This buffer copying impairs transmit performance on slower systems but can't -be avoided. On faster machines (e.g. a Pentium II), the performance +be avoided. +On faster machines (e.g. a Pentium II), the performance impact is much less noticable. |