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authorwpaul <wpaul@FreeBSD.org>1999-09-22 19:46:14 +0000
committerwpaul <wpaul@FreeBSD.org>1999-09-22 19:46:14 +0000
commit9e9ee6a9d861a3edf3d0726e5344af5760250c3b (patch)
treef5b347a591b943eaac4fcf783c089322bdf30eb2 /share/man/man4/vr.4
parent79bc9f0914323ba50b176fc8572d2038bc0bac95 (diff)
downloadFreeBSD-src-9e9ee6a9d861a3edf3d0726e5344af5760250c3b.zip
FreeBSD-src-9e9ee6a9d861a3edf3d0726e5344af5760250c3b.tar.gz
Mention in the documentation that the AOpen/Acer ALN-320 is a supported
ethernet card (PCI, VIA Rhine II chipset).
Diffstat (limited to 'share/man/man4/vr.4')
-rw-r--r--share/man/man4/vr.415
1 files changed, 8 insertions, 7 deletions
diff --git a/share/man/man4/vr.4 b/share/man/man4/vr.4
index 8100bfe..7b914e8 100644
--- a/share/man/man4/vr.4
+++ b/share/man/man4/vr.4
@@ -45,15 +45,16 @@ The
driver provides support for PCI ethernet adapters and embedded
controllers based on the VIA Technologies VT3043 Rhine I and
VT86C100A Rhine II fast ethernet controller chips. This includes
-the D-Link DFE530-TX and various other commodity fast ethernet
+the D-Link DFE530-TX, the Hawking Technologies PN102TX, the
+AOpen/Acer ALN-320, and various other commodity fast ethernet
cards.
.Pp
-The VIA Rhine chips use bus master DMA and have a software interface
-designed to resemble that of the DEC 21x4x "tulip" chips. The major
-differences are that the receive filter in the Rhine chips is
-much simpler and is programmed through registers rather than by
-downloading a special setup frame through the transmit DMA engine,
-and that transmit and receive DMA buffers must be longword
+The VIA Rhine chips use bus master DMA and have a descriptor layout
+designed to resemble that of the DEC 21x4x "tulip" chips. The register
+layout is different however and the receive filter in the Rhine chips
+is much simpler and is programmed through registers rather than by
+downloading a special setup frame through the transmit DMA engine.
+Transmit and receive DMA buffers must be longword
aligned. The Rhine chips are meant to be interfaced with external
physical layer devices via an MII bus. They support both
10 and 100Mbps speeds in either full or half duplex.
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