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author | nsouch <nsouch@FreeBSD.org> | 1999-01-23 14:01:55 +0000 |
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committer | nsouch <nsouch@FreeBSD.org> | 1999-01-23 14:01:55 +0000 |
commit | d0d84dd5f2758fa46f7a2b06ce178d8339f60c96 (patch) | |
tree | c379fa59e13022be9f2c0f03164a7d67da5b9e32 /share/man/man4/ppbus.4 | |
parent | f1013afa3edcf284685e4f5da462718e707a5ad5 (diff) | |
download | FreeBSD-src-d0d84dd5f2758fa46f7a2b06ce178d8339f60c96.zip FreeBSD-src-d0d84dd5f2758fa46f7a2b06ce178d8339f60c96.tar.gz |
Remove imm.4, merged with vpo.4
Fix vpo.4 manpage generation in Makefile
Fix bootflags bits description in ppc.4
Diffstat (limited to 'share/man/man4/ppbus.4')
-rw-r--r-- | share/man/man4/ppbus.4 | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/share/man/man4/ppbus.4 b/share/man/man4/ppbus.4 index 74a06bd..3b012f4 100644 --- a/share/man/man4/ppbus.4 +++ b/share/man/man4/ppbus.4 @@ -155,6 +155,26 @@ DMA as well as programmed I/O for the host register interface. The EPP protocol was originally developed as a means to provide a high performance parallel port link that would still be compatible with the standard parallel port. +.Pp +The EPP mode has two types of cycle: address and data. What makes the +difference at hardware level is the strobe of the byte placed on the data +lines. Data are strobed with nAutofeed, addresses are strobed with +nSelectin signals. +.Pp +A particularity of the ISA implementation of the EPP protocol is that an +EPP cycle fits in an ISA cycle. In this fashion, parallel port peripherals can +operate at close to the same performance levels as an equivalent ISA plug-in +card. +.Pp +At software level, you may implement the protocol you wish, using data and +address cycles as you want. This is for the IEEE1284 compatible part. Then, +peripheral vendors may implement protocol handshake with the following +status lines: PError, nFault and Select. Try to know how these lines toggle +with your peripheral, allowing the peripheral to request more data, stop the +transfer and so on. +.Pp +At any time, the peripheral may interrupt the host with the nAck signal without +disturbing the current transfer. .Ss Mixed modes Some manufacturers, like SMC, have implemented chipsets that support mixed modes. With such chipsets, mode switching is available at any time by |