Remove single-space hard sentence breaks. These degrade the quality

of the typeset output, tend to make diffs harder to read and provide
bad examples for new-comers to mdoc.

1 files changed, 68 insertions, 34 deletions

diff --git a/share/man/man4/ppbus.4 b/share/man/man4/ppbus.4
index bf3458f..3ca7453 100644
--- a/share/man/man4/ppbus.4
+++ b/share/man/man4/ppbus.4
@@ -98,9 +98,11 @@ ppc makes chipset detection and initialization and then calls ppbus attach
 functions to initialize the ppbus system.
 .Sh PARALLEL PORT MODEL
 The logical parallel port model chosen for the ppbus system is the PC's
-parallel port model. Consequently, for the i386 implementation of ppbus,
+parallel port model.
+Consequently, for the i386 implementation of ppbus,
 most of the services provided by ppc are macros for inb()
-and outb() calls. But, for an other architecture, accesses to one of our logical
+and outb() calls.
+But, for an other architecture, accesses to one of our logical
 registers (data, status, control...) may require more than one I/O access.
 .Ss Description
 The parallel port may operate in the following modes:
@@ -125,21 +127,26 @@ checked for no errors and that it is not busy, and then a data Strobe is
 generated by the software to clock the data to the printer.
 .Pp
 Many I/O controllers have implemented a mode that uses a FIFO buffer to
-transfer data with the Compatibility mode protocol. This mode is referred to as
+transfer data with the Compatibility mode protocol.
+This mode is referred to as
 "Fast Centronics" or "Parallel Port FIFO mode".
 .Ss Bidirectional mode
 The NIBBLE mode is the most common way to get reverse channel data from a
-printer or peripheral. Combined with the standard host to printer mode, it
+printer or peripheral.
+Combined with the standard host to printer mode, it
 provides a complete bidirectional channel.
 .Pp
-In this mode, outputs are 8-bits long. Inputs are accomplished by reading
+In this mode, outputs are 8-bits long.
+Inputs are accomplished by reading
 4 of the 8 bits of the status register.
 .Ss Byte mode
-In this mode, the data register is used either for outputs and inputs. Then,
+In this mode, the data register is used either for outputs and inputs.
+Then,
 any transfer is 8-bits long.
 .Ss Extended Capability Port mode
 The ECP protocol was proposed as an advanced mode for communication with
-printer and scanner type peripherals. Like the EPP protocol, ECP mode provides
+printer and scanner type peripherals.
+Like the EPP protocol, ECP mode provides
 for a high performance bidirectional communication path between the host
 adapter and the peripheral.
 .Pp
@@ -157,20 +164,25 @@ The EPP protocol was originally developed as a means to provide a high
 performance parallel port link that would still be compatible with the
 standard parallel port.
 .Pp
-The EPP mode has two types of cycle: address and data. What makes the 
+The EPP mode has two types of cycle: address and data.
+What makes the 
 difference at hardware level is the strobe of the byte placed on the data
-lines. Data are strobed with nAutofeed, addresses are strobed with 
+lines.
+Data are strobed with nAutofeed, addresses are strobed with 
 nSelectin signals.
 .Pp
 A particularity of the ISA implementation of the EPP protocol is that an 
-EPP cycle fits in an ISA cycle. In this fashion, parallel port peripherals can
+EPP cycle fits in an ISA cycle.
+In this fashion, parallel port peripherals can
 operate at close to the same performance levels as an equivalent ISA plug-in
 card.
 .Pp
 At software level, you may implement the protocol you wish, using data and
-address cycles as you want. This is for the IEEE1284 compatible part. Then,
+address cycles as you want. This is for the IEEE1284 compatible part.
+Then,
 peripheral vendors may implement protocol handshake with the following 
-status lines: PError, nFault and Select. Try to know how these lines toggle
+status lines: PError, nFault and Select.
+Try to know how these lines toggle
 with your peripheral, allowing the peripheral to request more data, stop the
 transfer and so on.
 .Pp
@@ -178,41 +190,51 @@ At any time, the peripheral may interrupt the host with the nAck signal without
 disturbing the current transfer.
 .Ss Mixed modes
 Some manufacturers, like SMC, have implemented chipsets that support mixed
-modes. With such chipsets, mode switching is available at any time by
+modes.
+With such chipsets, mode switching is available at any time by
 accessing the extended control register.
 .Sh IEEE1284-1994 Standard
 .Ss Background
 This standard is also named "IEEE Standard Signaling Method for a
 Bidirectional Parallel Peripheral Interface for Personal Computers". It
 defines a signaling method for asynchronous, fully interlocked, bidirectional
-parallel communications between hosts and printers or other peripherals. It
+parallel communications between hosts and printers or other peripherals.
+It
 also specifies a format for a peripheral identification string and a method of
 returning this string to the host outside of the bidirectional data stream.
 .Pp
 This standard is architecture independent and only specifies dialog handshake
-at signal level. One should refer to architecture specific documentation in
+at signal level.
+One should refer to architecture specific documentation in
 order to manipulate machine dependent registers, mapped memory or other
 methods to control these signals.
 .Pp
 The IEEE1284 protocol is fully oriented with all supported parallel port
-modes. The computer acts as master and the peripheral as slave.
+modes.
+The computer acts as master and the peripheral as slave.
 .Pp
-Any transfer is defined as a finite state automate. It allows software to
+Any transfer is defined as a finite state automate.
+It allows software to
 properly manage the fully interlocked scheme of the signaling method.
 The compatible mode is supported "as is" without any negotiation because it
-is compatible. Any other mode must be firstly negotiated by the host to check
+is compatible.
+Any other mode must be firstly negotiated by the host to check
 it is supported by the peripheral, then to enter one of the forward idle
 states.
 .Pp
-At any time, the slave may want to send data to the host. This is only
+At any time, the slave may want to send data to the host.
+This is only
 possible from forward idle states (nibble, byte, ecp...). So, the
 host must have previously negotiated to permit the peripheral to
-request transfer. Interrupt lines may be dedicated to the requesting signals
+request transfer.
+Interrupt lines may be dedicated to the requesting signals
 to prevent time consuming polling methods.
 .Pp
-But peripheral requests are only a hint to the master host. If the host
+But peripheral requests are only a hint to the master host.
+If the host
 accepts the transfer, it must firstly negotiate the reverse mode and then
-starts the transfer. At any time during reverse transfer, the host may
+starts the transfer.
+At any time during reverse transfer, the host may
 terminate the transfer or the slave may drive wires to signal that no more
 data is available.
 .Ss Implementation
@@ -221,14 +243,17 @@ as a set of procedures that perform high level functions like negotiation,
 termination, transfer in any mode without bothering you with low level
 characteristics of the standard.
 .Pp
-IEEE1284 interacts with the ppbus system as least as possible. That means
+IEEE1284 interacts with the ppbus system as least as possible.
+That means
 you still have to request the ppbus when you want to access it, the negotiate
-function doesn't do it for you. And of course, release it later.
+function doesn't do it for you.
+And of course, release it later.
 .Sh ARCHITECTURE
 .Ss adapter, ppbus and device layers
 First, there is the
 .Em adapter
-layer, the lowest of the ppbus system. It provides
+layer, the lowest of the ppbus system.
+It provides
 chipset abstraction throw a set of low level functions that maps the logical
 model to the underlying hardware.
 .Pp
@@ -255,7 +280,8 @@ one, current and available modes are separated.
 .Pp
 With this level of abstraction a particular chipset may commute from any
 native mode the any other mode emulated with extended modes without
-disturbing upper layers. For example, most chipsets support NIBBLE mode as
+disturbing upper layers.
+For example, most chipsets support NIBBLE mode as
 native and emulated with ECP and/or EPP.
 .Pp
 This architecture should support IEEE1284-1994 modes.
@@ -263,7 +289,8 @@ This architecture should support IEEE1284-1994 modes.
 .Ss The boot process
 The boot process starts with the probe phasis of the
 .Xr ppc 4
-driver during ISA bus (PC architecture) initialization. During attachment of
+driver during ISA bus (PC architecture) initialization.
+During attachment of
 the ppc driver, a new ppbus structure is allocated, then probe and attachment
 for this new bus node are called.
 .Pp
@@ -273,10 +300,12 @@ draft from (c)1993-4 Microsoft Corporation)
 then probes and attaches known device drivers.
 .Pp
 During probe, device drivers are supposed to request the ppbus and try to
-set their operating mode. This mode will be saved in the context structure and
+set their operating mode.
+This mode will be saved in the context structure and
 returned each time the driver requests the ppbus.
 .Ss Bus allocation and interrupts
-ppbus allocation is mandatory not to corrupt I/O of other devices. An other
+ppbus allocation is mandatory not to corrupt I/O of other devices.
+An other
 usage of ppbus allocation is to reserve the port and receive incoming
 interrupts.
 .Pp
@@ -285,19 +314,24 @@ newbus
 .Fn BUS_SETUP_INTR
 and
 .Fn BUS_TEARDOWN_INTR
-functions. But, in order to attach a handler, drivers must
-own the bus. Consequently, a ppbus request is mandatory in order to call the above
+functions.
+But, in order to attach a handler, drivers must
+own the bus.
+Consequently, a ppbus request is mandatory in order to call the above
 functions (see existing drivers for more info). Note that the interrupt handler
 is automatically released when the ppbus is released.
 .Ss Microsequences
 .Em Microsequences
 is a general purpose mechanism to allow fast low-level
-manipulation of the parallel port. Microsequences may be used to do either
-standard (in IEEE1284 modes) or non-standard transfers. The philosophy of
+manipulation of the parallel port.
+Microsequences may be used to do either
+standard (in IEEE1284 modes) or non-standard transfers.
+The philosophy of
 microsequences is to avoid the overhead of the ppbus layer and do most of
 the job at adapter level.
 .Pp
-A microsequence is an array of opcodes and parameters. Each opcode codes an
+A microsequence is an array of opcodes and parameters.
+Each opcode codes an
 operation (opcodes are described in
 .Xr microseq 9 ).
 Standard I/O operations are implemented at ppbus level whereas basic I/O