Spelling and grammar fixes.

PR:		docs/10401

1 files changed, 23 insertions, 23 deletions

diff --git a/share/man/man4/ppbus.4 b/share/man/man4/ppbus.4
index 3b012f4..29b666d 100644
--- a/share/man/man4/ppbus.4
+++ b/share/man/man4/ppbus.4
@@ -57,7 +57,7 @@ mechanism to allow various devices to share the same parallel port
 .It
 a user interface named
 .Xr ppi 4
-that allows parallel port access from outside the kernel without confliting
+that allows parallel port access from outside the kernel without conflicting
 with kernel-in drivers.
 .El
 .Ss Developing new drivers
@@ -68,7 +68,7 @@ and non-standard software:
 .Bl -column "Driver" -compact
 .It Em Driver Ta Em Description
 .It Sy vpo Ta "VPI0 parallel to Adaptec AIC-7110 SCSI controller driver."
-It uses standard and non-standard parallel port accesses
+It uses standard and non-standard parallel port accesses.
 .It Sy ppi Ta "Parallel port interface for general I/O"
 .It Sy pps Ta "Pulse per second Timing Interface"
 .It Sy lpbb Ta "Philips official parallel port I2C bit-banging interface"
@@ -93,7 +93,7 @@ Parallel port chipset support is provided by
 The ppbus system provides functions and macros to allocate a new
 parallel port bus, then initialize it and upper peripheral device drivers.
 .Pp
-ppc makes chipset detection and initialisation and then calls ppbus attach
+ppc makes chipset detection and initialization and then calls ppbus attach
 functions to initialize the ppbus system.
 .Sh PARALLEL PORT MODEL
 The logical parallel port model chosen for the ppbus system is the PC's
@@ -121,7 +121,7 @@ mixed ECP+EPP or ECP+PS/2 modes
 This mode defines the protocol used by most PCs to transfer data to a printer.
 In this mode, data is placed on the port's data lines, the printer status is
 checked for no errors and that it is not busy, and then a data Strobe is
-generated by the sofware to clock the data to the printer.
+generated by the software to clock the data to the printer.
 .Pp
 Many I/O controllers have implemented a mode that uses a FIFO buffer to
 transfer data with the Compatibility mode protocol. This mode is referred to as
@@ -183,45 +183,45 @@ accessing the extended control register.
 .Ss Background
 This standard is also named "IEEE Standard Signaling Method for a
 Bidirectional Parallel Peripheral Interface for Personal Computers". It
-defines a signaling method for asynchroneous, fully interlocked, bidirectional
+defines a signaling method for asynchronous, fully interlocked, bidirectional
 parallel communications between hosts and printers or other peripherals. It
 also specifies a format for a peripheral identification string and a method of
 returning this string to the host outside of the bidirectional data stream.
 .Pp
-This standard is architecture independent and only specifiy dialog handshake
-at signal level. One should refer to any architecture specific document in
-order to manipulate machine dependent registers, mapped memory or whatelse
-to control these signals.
+This standard is architecture independent and only specifies dialog handshake
+at signal level. One should refer to architecture specific documentation in
+order to manipulate machine dependent registers, mapped memory or other
+methods to control these signals.
 .Pp
 The IEEE1284 protocol is fully oriented with all supported parallel port
 modes. The computer acts as master and the peripheral as slave.
 .Pp
 Any transfer is defined as a finite state automate. It allows software to
 properly manage the fully interlocked scheme of the signaling method.
-The compatible mode is supported "as is" without any negociation because it
-is compatible. Any other mode must be firstly negociated by the host to check
+The compatible mode is supported "as is" without any negotiation because it
+is compatible. Any other mode must be firstly negotiated by the host to check
 it is supported by the peripheral, then to enter one of the forward idle
 states.
 .Pp
 At any time, the slave may want to send data to the host. This is only
 possible from forward idle states (nibble, byte, ecp...). So, the
-host must have previously negociated to permit the peripheral to
+host must have previously negotiated to permit the peripheral to
 request transfer. Interrupt lines may be dedicated to the requesting signals
 to prevent time consuming polling methods.
 .Pp
 But peripheral requests are only a hint to the master host. If the host
-accepts the transfer, it must firstly negociate the reverse mode and then
+accepts the transfer, it must firstly negotiate the reverse mode and then
 starts the transfer. At any time during reverse transfer, the host may
 terminate the transfer or the slave may drive wires to signal that no more
 data is available.
 .Ss Implementation
 IEEE1284 Standard support has been implemented at the top of the ppbus system
-as a set of procedures that perform high level functions like negociation,
+as a set of procedures that perform high level functions like negotiation,
 termination, transfer in any mode without bothering you with low level
-caracteristics of the stantdard.
+characteristics of the standard.
 .Pp
 IEEE1284 interacts with the ppbus system as least as possible. That means
-you still have to request the ppbus when you want to access it, the negociate
+you still have to request the ppbus when you want to access it, the negotiate
 function doesn't do it for you. And of course, release it later.
 .Sh ARCHITECTURE
 .Ss adapter, ppbus and device layers
@@ -243,7 +243,7 @@ manage devices linked to ppbus
 propose an arch-independent interface to access the hardware layer.
 .El
 .Pp
-Finaly, the
+Finally, the
 .Em device
 layer gathers the parallel peripheral device drivers.
 .Pp
@@ -253,22 +253,22 @@ info shared among different layers.
 .Pp
 See description of these structures in
 .Xr ppbconf 9 .
-.Ss Parallel modes managment
-We have to differenciate operating modes at various ppbus system layers.
+.Ss Parallel modes management
+We have to differentiate operating modes at various ppbus system layers.
 Actually, ppbus and adapter operating modes on one hands and for each
-one, current and available modes are seperated.
+one, current and available modes are separated.
 .Pp
 With this level of abstraction a particular chipset may commute from any
 native mode the any other mode emulated with extended modes without
 disturbing upper layers. For example, most chipsets support NIBBLE mode as
 native and emulated with ECP and/or EPP.
 .Pp
-This achitecture should support IEEE1284-1994 modes.
+This architecture should support IEEE1284-1994 modes.
 .Sh FEATURES
 .Ss The boot process
 The boot process starts with the probe phasis of the
 .Xr ppc 4
-driver during ISA bus (PC architecture) initialisation. During attachment of
+driver during ISA bus (PC architecture) initialization. During attachment of
 the ppc driver, a new ppbus structure is allocated, initialized
 (linked to the adapter structure) then passed to the function
 .Fn ppb_attachdevs "struct ppb_data *ppb" .
@@ -306,7 +306,7 @@ A microsequence is an array of opcodes and parameters. Each opcode codes an
 operation (opcodes are described in
 .Xr microseq 9 ).
 Standard I/O operations are implemented at ppbus level whereas basic I/O
-operations and microseq langage are coded at adapter level for efficiency.
+operations and microseq language are coded at adapter level for efficiency.
 .Pp
 As an example, the
 .Xr vpo 4