Document support for Intel Enhanced Speedstep Tech interface

of cpufreq(4) via a new man page est(4)

Document the two exposed tuneables of est(4).

I'd appreciate more reviews of content if possible.  I gleaned
the information contained herein from sys/x86/cpufreq/est.c and
the Intel reference documentation

Reviewed by:    wblock hrs gjb
MFC after:      2 weeks

1 files changed, 100 insertions, 0 deletions

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+.\"
+.\" Copyright (c) 2012 Sean Bruno <sbruno@freebsd.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd June 12, 2012
+.Dt EST 4
+.Os
+.Sh NAME
+.Nm est
+.Nd Enhanced Speedstep Technology
+.Sh SYNOPSIS
+To compile this capability into your kernel
+place the following line in your kernel
+configuration file:
+.Bd -ragged -offset indent
+.Cd "device cpufreq"
+.Ed
+.Sh DESCRIPTION
+The
+.Nm
+interface provides support for the Intel Enhanced Speedstep Technology.
+.Pp
+Note that
+.Nm
+capabilities are automatically loaded by the
+.Xr cpufreq 4
+driver.
+.Sh LOADER TUNABLES
+The
+.Nm
+interface is intended to allow
+.Xr cpufreq 4
+to access and implement Intel Enhanced SpeedStep Technology via
+.Xr acpi 4
+and the acpi_perf interface accessors.
+If the default settings are not optimal, the following sysctls can be
+used to modify or monitor
+.Nm
+behavior.
+.Bl -tag -width indent
+.It hw.est.msr_info
+Attempt to infer information from direct probing of the msr.
+Should only be used in diagnostic cases 
+.Pq default 0
+.It hw.est.strict
+Do not allow different cpus to be set to different frequencies.
+It appears that this will only work on i386 systems 
+.Pq default 0
+.El
+.Sh DIAGNOSTICS
+.Bl -diag
+.It "est%d: <Enhanced SpeedStep Frequency Control> on cpu%d"
+.Pp
+Indicates normal startup of this interface.
+.It "est: CPU supports Enhanced Speedstep, but is not recognized."
+.It "est: cpu_vendor GenuineIntel, msr 471c471c0600471c"
+.It "device_attach: est%d attach returned 6"
+.Pp
+Indicates all attempts to attach to this interface have failed.
+This usually indicates an improper BIOS setting restricting O/S
+control of the CPU speeds.
+Consult your BIOS documentation for more details.
+.El
+.Sh COMPATIBILITY
+.Nm
+is only found on supported Intel CPUs.
+.Sh SEE ALSO
+.Xr cpufreq 4
+.Sh SUPPORT
+For general information and support,
+go to the Intel 64 and IA-32 Architectures Software Developer
+Manuals site.
+.Pa http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
+.Sh AUTHORS
+.Pp
+This manual page was written by
+.An Sean Bruno Aq sbruno@FreeBSD.org .