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| author | dim <dim@FreeBSD.org> | 2017-09-05 17:32:14 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2017-09-05 17:32:14 +0000 |
| commit | dee4e67672c3fcd741bc71849cf462fd38044dd7 (patch) | |
| tree | 9a97397daf801ab0293a327a00b4aaa0fe51e302 /lib | |
| parent | b3ef7b369b144d0f58083c3965742583f3ab7190 (diff) | |
| download | FreeBSD-src-dee4e67672c3fcd741bc71849cf462fd38044dd7.zip FreeBSD-src-dee4e67672c3fcd741bc71849cf462fd38044dd7.tar.gz | |
MFC r323001:
In compiler-rt, a few assembler implementations for i386 floating point
conversion functions use SSE2 instructions, but these are not guarded by
#ifdef __SSE2__, and there is no implementation using general purpose
registers. For these functions, use the generic C variants instead,
otherwise they will cause SIGILL on older processors.
Approved by: re (kib)
Reported by: bsdpr@phoe.frmug.org
PR: 221733
MFC r323014:
Follow-up to r323001: if the actually selected CPUTYPE is capable of
SSE2 instructions, we can use them.
Suggested by: jkim
PR: 221733
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/libcompiler_rt/Makefile | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/lib/libcompiler_rt/Makefile b/lib/libcompiler_rt/Makefile index 8c560d7..7ccccca 100644 --- a/lib/libcompiler_rt/Makefile +++ b/lib/libcompiler_rt/Makefile @@ -65,15 +65,9 @@ SRCF= absvdi2 \ fixunsxfti \ fixxfdi \ fixxfti \ - floatdidf \ - floatdisf \ - floatdixf \ floattidf \ floattisf \ floattixf \ - floatundidf \ - floatundisf \ - floatundixf \ floatunsidf \ floatunsisf \ floatuntidf \ @@ -126,6 +120,23 @@ SRCF= absvdi2 \ umoddi3 \ umodti3 +# Avoid using SSE2 instructions on i386, if unsupported. +.if ${MACHINE_CPUARCH} == "i386" && empty(MACHINE_CPU:Msse2) +SRCS+= floatdidf.c +SRCS+= floatdisf.c +SRCS+= floatdixf.c +SRCS+= floatundidf.c +SRCS+= floatundisf.c +SRCS+= floatundixf.c +.else +SRCF+= floatdidf +SRCF+= floatdisf +SRCF+= floatdixf +SRCF+= floatundidf +SRCF+= floatundisf +SRCF+= floatundixf +.endif + # These are already shipped by libc.a on arm and mips .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips" SRCF+= adddf3 \ |
