- Document event numbers.

- Correct misspellings of two event names.

1 files changed, 108 insertions, 39 deletions

diff --git a/lib/libpmc/pmc.p6.3 b/lib/libpmc/pmc.p6.3
index 55bbc64..1b4fbff 100644
--- a/lib/libpmc/pmc.p6.3
+++ b/lib/libpmc/pmc.p6.3
@@ -121,75 +121,86 @@ qualifiers are specified, the default is to enable both.
 The event specifiers supported by Intel P6 PMCs are:
 .Bl -tag -width indent
 .It Li p6-baclears
+.Pq Event E6H
 Count the number of times a static branch prediction was made by the
 branch decoder because the BTB did not have a prediction.
 .It Li p6-br-bac-missp-exec
-.Pq Tn "Pentium M"
+.Pq Event 8AH , Tn "Pentium M"
 Count the number of branch instructions executed that where
 mispredicted at the Front End (BAC).
 .It Li p6-br-bogus
+.Pq Event E4H
 Count the number of bogus branches.
 .It Li p6-br-call-exec
-.Pq Tn "Pentium M"
+.Pq Event 92H , Tn "Pentium M"
 Count the number of call instructions executed.
 .It Li p6-br-call-missp-exec
-.Pq Tn "Pentium M"
+.Pq Event 93H , Tn "Pentium M"
 Count the number of call instructions executed that were mispredicted.
 .It Li p6-br-cnd-exec
-.Pq Tn "Pentium M"
+.Pq Event 8BH , Tn "Pentium M"
 Count the number of conditional branch instructions executed.
 .It Li p6-br-cnd-missp-exec
-.Pq Tn "Pentium M"
+.Pq Event 8CH , Tn "Pentium M"
 Count the number of conditional branch instructions executed that were
 mispredicted.
 .It Li p6-br-ind-call-exec
-.Pq Tn "Pentium M"
+.Pq Event 94H , Tn "Pentium M"
 Count the number of indirect call instructions executed.
 .It Li p6-br-ind-exec
-.Pq Tn "Pentium M"
+.Pq Event 8DH , Tn "Pentium M"
 Count the number of indirect branch instructions executed.
 .It Li p6-br-ind-missp-exec
-.Pq Tn "Pentium M"
+.Pq Event 8EH , Tn "Pentium M"
 Count the number of indirect branch instructions executed that were
 mispredicted.
 .It Li p6-br-inst-decoded
+.Pq Event E0H
 Count the number of branch instructions decoded.
 .It Li p6-br-inst-exec
-.Pq Tn "Pentium M"
+.Pq Event 88H , Tn "Pentium M"
 Count the number of branch instructions executed but necessarily retired.
 .It Li p6-br-inst-retired
+.Pq Event C4H
 Count the number of branch instructions retired.
 .It Li p6-br-miss-pred-retired
+.Pq Event C5H
 Count the number of mispredicted branch instructions retired.
 .It Li p6-br-miss-pred-taken-ret
+.Pq Event C9H
 Count the number of taken mispredicted branches retired.
 .It Li p6-br-missp-exec
-.Pq Tn "Pentium M"
+.Pq Event 89H , Tn "Pentium M"
 Count the number of branch instructions executed that were
 mispredicted at execution.
 .It Li p6-br-ret-bac-missp-exec
-.Pq Tn "Pentium M"
+.Pq Event 91H , Tn "Pentium M"
 Count the number of return instructions executed that were
 mispredicted at the Front End (BAC).
 .It Li p6-br-ret-exec
-.Pq Tn "Pentium M"
+.Pq Event 8FH , Tn "Pentium M"
 Count the number of return instructions executed.
 .It Li p6-br-ret-missp-exec
-.Pq Tn "Pentium M"
+.Pq Event 90H , Tn "Pentium M"
 Count the number of return instructions executed that were
 mispredicted at execution.
 .It Li p6-br-taken-retired
+.Pq Event C9H
 Count the number of taken branches retired.
 .It Li p6-btb-misses
+.Pq Event E2H
 Count the number of branches for which the BTB did not produce a
 prediction.
 .It Li p6-bus-bnr-drv
+.Pq Event 61H
 Count the number of bus clock cycles during which this processor is
 driving the BNR# pin.
 .It Li p6-bus-data-rcv
+.Pq Event 64H
 Count the number of bus clock cycles during which this processor is
 receiving data.
 .It Li p6-bus-drdy-clocks Op Li ,umask= Ns Ar qualifier
+.Pq Event 62H
 Count the number of clocks during which DRDY# is asserted.
 An additional qualifier may be specified, and comprises one of the
 following keywords:
@@ -203,12 +214,15 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-hit-drv
+.Pq Event 7AH
 Count the number of bus clock cycles during which this processor is
 driving the HIT# pin.
 .It Li p6-bus-hitm-drv
+.Pq Event 7BH
 Count the number of bus clock cycles during which this processor is
 driving the HITM# pin.
 .It Li p6-bus-lock-clocks Op Li ,umask= Ns Ar qualifier
+.Pq Event 63H
 Count the number of clocks during with LOCK# is asserted on the
 external system bus.
 An additional qualifier may be specified and comprises one of the following
@@ -223,10 +237,13 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-req-outstanding
+.Pq Event 60H
 Count the number of bus requests outstanding in any given cycle.
 .It Li p6-bus-snoop-stall
+.Pq Event 7EH
 Count the number of clock cycles during which the bus is snoop stalled.
 .It Li p6-bus-tran-any Op Li ,umask= Ns Ar qualifier
+.Pq Event 70H
 Count the number of completed bus transactions of any kind.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -240,6 +257,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-tran-brd Op Li ,umask= Ns Ar qualifier
+.Pq Event 65H
 Count the number of burst read transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -253,6 +271,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-tran-burst Op Li ,umask= Ns Ar qualifier
+.Pq Event 6EH
 Count the number of completed burst transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -266,6 +285,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-tran-def Op Li ,umask= Ns Ar qualifier
+.Pq Event 6DH
 Count the number of completed deferred transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -279,6 +299,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-tran-ifetch Op Li ,umask= Ns Ar qualifier
+.Pq Event 68H
 Count the number of completed instruction fetch transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -292,6 +313,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-tran-inval Op Li ,umask= Ns Ar qualifier
+.Pq Event 69H
 Count the number of completed invalidate transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -305,6 +327,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-tran-mem Op Li ,umask= Ns Ar qualifier
+.Pq Event 6FH
 Count the number of completed memory transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -318,6 +341,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-tran-pwr Op Li ,umask= Ns Ar qualifier
+.Pq Event 6AH
 Count the number of completed partial write transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -331,6 +355,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-tran-rfo Op Li ,umask= Ns Ar qualifier
+.Pq Event 66H
 Count the number of completed read-for-ownership transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -344,6 +369,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-trans-io Op Li ,umask= Ns Ar qualifier
+.Pq Event 6CH
 Count the number of completed I/O transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -357,6 +383,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-trans-p Op Li ,umask= Ns Ar qualifier
+.Pq Event 6BH
 Count the number of completed partial transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -370,6 +397,7 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-bus-trans-wb Op Li ,umask= Ns Ar qualifier
+.Pq Event 67H
 Count the number of completed write-back transactions.
 An additional qualifier may be specified and comprises one of the following
 keywords:
@@ -383,44 +411,54 @@ Count transactions generated by this processor.
 .Pp
 The default is to count operations generated by this processor.
 .It Li p6-cpu-clk-unhalted
+.Pq Event 79H
 Count the number of cycles during with the processor was not halted.
 .Pp
 .Pq Tn "Pentium M"
 Count the number of cycles during with the processor was not halted
 and not in a thermal trip.
 .It Li p6-cycles-div-busy
+.Pq Event 14H
 Count the number of cycles during which the divider is busy and cannot
 accept new divides.
 This event is only allocated on counter 0.
 .It Li p6-cycles-in-pending-and-masked
+.Pq Event C7H
 Count the number of processor cycles for which interrupts were
 disabled and interrupts were pending.
 .It Li p6-cycles-int-masked
+.Pq Event C6H
 Count the number of processor cycles for which interrupts were
 disabled.
 .It Li p6-data-mem-refs
+.Pq Event 43H
 Count all loads and all stores using any memory type, including
 internal retries.
 Each part of a split store is counted separately.
 .It Li p6-dcu-lines-in
+.Pq Event 45H
 Count the total lines allocated in the data cache unit.
 .It Li p6-dcu-m-lines-in
+.Pq Event 46H
 Count the number of M state lines allocated in the data cache unit.
 .It Li p6-dcu-m-lines-out
+.Pq Event 47H
 Count the number of M state lines evicted from the data cache unit.
 .It Li p6-dcu-miss-outstanding
+.Pq Event 48H
 Count the weighted number of cycles while a data cache unit miss is
 outstanding, incremented by the number of outstanding cache misses at
 any time.
 .It Li p6-div
+.Pq Event 13H
 Count the number of integer and floating-point divides including
 speculative divides.
 This event is only allocated on counter 1.
 .It Li p6-emon-esp-uops
-.Pq Tn "Pentium M"
+.Pq Event D7H , Tn "Pentium M"
 Count the total number of micro-ops.
 .It Li p6-emon-est-trans Op Li ,umask= Ns Ar qualifier
-.Pq Tn "Pentium M"
+.Pq Event 58H , Tn "Pentium M"
 Count the number of
 .Tn "Enhanced Intel SpeedStep"
 transitions.
@@ -436,7 +474,7 @@ Count only frequency transitions.
 .Pp
 The default is to count all transitions.
 .It Li p6-emon-fused-uops-ret Op Li ,umask= Ns Ar qualifier
-.Pq Tn "Pentium M"
+.Pq Event DAH , Tn "Pentium M"
 Count the number of retired fused micro-ops.
 An additional qualifier may be specified, and may be one of the
 following keywords:
@@ -452,7 +490,7 @@ Count only STD/STA micro-ops.
 .Pp
 The default is to count all fused micro-ops.
 .It Li p6-emon-kni-comp-inst-ret
-.Pq Tn "Pentium III"
+.Pq Event D9H , Tn "Pentium III"
 Count the number of SSE computational instructions retired.
 An additional qualifier may be specified, and comprises one of the
 following keywords:
@@ -466,7 +504,7 @@ Count scalar operations only.
 .Pp
 The default is to count packed and scalar operations.
 .It Li p6-emon-kni-inst-retired Op Li ,umask= Ns Ar qualifier
-.Pq Tn "Pentium III"
+.Pq Event D8H , Tn "Pentium III"
 Count the number of SSE instructions retired.
 An additional qualifier may be specified, and comprises one of the
 following keywords:
@@ -480,6 +518,7 @@ Count scalar operations only.
 .Pp
 The default is to count packed and scalar operations.
 .It Li p6-emon-kni-pref-dispatched Op Li ,umask= Ns Ar qualifier
+.Pq Event 07H
 .Pq Tn "Pentium III"
 Count the number of SSE prefetch or weakly ordered instructions
 dispatched (including speculative prefetches).
@@ -499,7 +538,7 @@ Count weakly ordered stores.
 .Pp
 The default is to count non-temporal prefetches.
 .It Li p6-emon-kni-pref-miss Op Li ,umask= Ns Ar qualifier
-.Pq Tn "Pentium III"
+.Pq Event 4BH , Tn "Pentium III"
 Count the number of prefetch or weakly ordered instructions that miss
 all caches.
 An additional qualifier may be specified, and comprises one of the
@@ -518,18 +557,18 @@ Count weakly ordered stores.
 .Pp
 The default is to count non-temporal prefetches.
 .It Li p6-emon-pref-rqsts-dn
-.Pq Tn "Pentium M"
+.Pq Event F8H , Tn "Pentium M"
 Count the number of downward prefetches issued.
 .It Li p6-emon-pref-rqsts-up
-.Pq Tn "Pentium M"
+.Pq Event F0H , Tn "Pentium M"
 Count the number of upward prefetches issued.
 .It Li p6-emon-simd-instr-retired
-.Pq Tn "Pentium M"
+.Pq Event CEH , Tn "Pentium M"
 Count the number of retired
 .Tn MMX
 instructions.
 .It Li p6-emon-sse-sse2-comp-inst-retired Op Li ,umask= Ns Ar qualifier
-.Pq Tn "Pentium M"
+.Pq Event D9H , Tn "Pentium M"
 Count the number of computational SSE instructions retired.
 An additional qualifier may be specified and can be one of the
 following keywords:
@@ -547,8 +586,7 @@ Count SSE2 scalar-double instructions.
 .Pp
 The default is to count SSE packed-single instructions.
 .It Li p6-emon-sse-sse2-inst-retired Op Li ,umask= Ns Ar qualifer
-.Pp
-.Pq Tn "Pentium M"
+.Pq Event D8H , Tn "Pentium M"
 Count the number of SSE instructions retired.
 An additional qualifier can be specified, and can be one of the
 following keywords:
@@ -566,28 +604,31 @@ Count SSE2 scalar-double instructions.
 .Pp
 The default is to count SSE packed-single instructions.
 .It Li p6-emon-synch-uops
-.Pq Tn "Pentium M"
+.Pq Event D3H , Tn "Pentium M"
 Count the number of sync micro-ops.
 .It Li p6-emon-thermal-trip
-.Pq Tn "Pentium M"
+.Pq Event 59H , Tn "Pentium M"
 Count the duration or occurrences of thermal trips.
 Use the
 .Dq Li edge
 qualifier to count occurrences of thermal trips.
 .It Li p6-emon-unfusion
-.Pq Tn "Pentium M"
+.Pq Event DBH , Tn "Pentium M"
 Count the number of unfusion events in the reorder buffer.
 .It Li p6-flops
+.Pq Event C1H
 Count the number of computational floating point operations retired.
 This event is only allocated on counter 0.
 .It Li p6-fp-assist
+.Pq Event 11H
 Count the number of floating point exceptions handled by microcode.
 This event is only allocated on counter 1.
 .It Li p6-fp-comps-ops-exe
+.Pq Event 10H
 Count the number of computation floating point operations executed.
 This event is only allocated on counter 0.
 .It Li p6-fp-mmx-trans Op Li ,umask= Ns Ar qualifier
-.Pq Tn "Pentium II" , Tn "Pentium III"
+.Pq Event CCH , Tn "Pentium II" , Tn "Pentium III"
 Count the number of transitions between MMX and floating-point
 instructions.
 An additional qualifier may be specified, and comprises one of the
@@ -602,30 +643,42 @@ Count transitions from floating-point instructions to MMX instructions.
 .Pp
 The default is to count MMX to floating-point transitions.
 .It Li p6-hw-int-rx
+.Pq Event C8H
 Count the number of hardware interrupts received.
-.It Li p6-ifu-fetch
+.It Li p6-ifu-ifetch
+.Pq Event 80H
 Count the number of instruction fetches, both cacheable and non-cacheable.
-.It Li p6-ifu-fetch-miss
+.It Li p6-ifu-ifetch-miss
+.Pq Event 81H
 Count the number of instruction fetch misses (i.e., those that produce
 memory accesses).
 .It Li p6-ifu-mem-stall
+.Pq Event 86H
 Count the number of cycles instruction fetch is stalled for any reason.
 .It Li p6-ild-stall
+.Pq Event 87H
 Count the number of cycles the instruction length decoder is stalled.
 .It Li p6-inst-decoded
+.Pq Event D0H
 Count the number of instructions decoded.
 .It Li p6-inst-retired
+.Pq Event C0H
 Count the number of instructions retired.
 .It Li p6-itlb-miss
+.Pq Event 85H
 Count the number of instruction TLB misses.
 .It Li p6-l2-ads
+.Pq Event 21H
 Count the number of L2 address strobes.
 .It Li p6-l2-dbus-busy
+.Pq Event 22H
 Count the number of cycles during which the L2 cache data bus was busy.
 .It Li p6-l2-dbus-busy-rd
+.Pq Event 23H
 Count the number of cycles during which the L2 cache data bus was busy
 transferring read data from L2 to the processor.
 .It Li p6-l2-ifetch Op Li ,umask= Ns Ar qualifier
+.Pq Event 28H
 Count the number of L2 instruction fetches.
 An additional qualifier may be specified and comprises a list of the following
 keywords separated by
@@ -645,6 +698,7 @@ Count operations affecting S (shared) state lines.
 .Pp
 The default is to count operations affecting all (MESI) state lines.
 .It Li p6-l2-ld Op Li ,umask= Ns Ar qualifier
+.Pq Event 29H
 Count the number of L2 data loads.
 An additional qualifier may be specified and comprises a list of the following
 keywords separated by
@@ -681,6 +735,7 @@ non-hardware-prefetch operations on all (MESI) state lines.
 .Pq Errata
 This event is affected by processor errata E53.
 .It Li p6-l2-lines-in Op Li ,umask= Ns Ar qualifier
+.Pq Event 24H
 Count the number of L2 lines allocated.
 An additional qualifier may be specified and comprises a list of the following
 keywords separated by
@@ -717,6 +772,7 @@ non-hardware-prefetch operations on all (MESI) state lines.
 .Pq Errata
 This event is affected by processor errata E45.
 .It Li p6-l2-lines-out Op Li ,umask= Ns Ar qualifier
+.Pq Event 26H
 Count the number of L2 lines evicted.
 An additional qualifier may be specified and comprises a list of the following
 keywords separated by
@@ -753,8 +809,10 @@ non-hardware-prefetch operations on all (MESI) state lines.
 .Pq Errata
 This event is affected by processor errata E45.
 .It Li p6-l2-m-lines-inm
+.Pq Event 25H
 Count the number of modified lines allocated in L2 cache.
 .It Li p6-l2-m-lines-outm Op Li ,umask= Ns Ar qualifier
+.Pq Event 27H
 Count the number of L2 M-state lines evicted.
 .Pp
 .Pq Tn "Pentium M"
@@ -777,6 +835,7 @@ non-hardware-prefetch operations.
 .Pq Errata
 This event is affected by processor errata E53.
 .It Li p6-l2-rqsts Op Li ,umask= Ns Ar qualifier
+.Pq Event 2EH
 Count the total number of L2 requests.
 An additional qualifier may be specified and comprises a list of the following
 keywords separated by
@@ -796,6 +855,7 @@ Count operations affecting S (shared) state lines.
 .Pp
 The default is to count operations affecting all (MESI) state lines.
 .It Li p6-l2-st
+.Pq Event 2AH
 Count the number of L2 data stores.
 An additional qualifier may be specified and comprises a list of the following
 keywords separated by
@@ -815,22 +875,25 @@ Count operations affecting S (shared) state lines.
 .Pp
 The default is to count operations affecting all (MESI) state lines.
 .It Li p6-ld-blocks
+.Pq Event 03H
 Count the number of load operations delayed due to store buffer blocks.
 .It Li p6-misalign-mem-ref
+.Pq Event 05H
 Count the number of misaligned data memory references (crossing a 64
 bit boundary).
 .It Li p6-mmx-assist
-.Pq Tn "Pentium II" , Tn "Pentium III"
+.Pq Event CDH , Tn "Pentium II" , Tn "Pentium III"
 Count the number of MMX assists executed.
 .It Li p6-mmx-instr-exec
+.Pq Event B0H
 .Pq Tn Celeron , Tn "Pentium II"
 Count the number of MMX instructions executed, except MOVQ and MOVD
 stores from register to memory.
 .It Li p6-mmx-instr-ret
-.Pq Tn "Pentium II"
+.Pq Event CEH , Tn "Pentium II"
 Count the number of MMX instructions retired.
 .It Li p6-mmx-instr-type-exec Op Li ,umask= Ns Ar qualifier
-.Pq Tn "Pentium II" , Tn "Pentium III"
+.Pq Event B3H , Tn "Pentium II" , Tn "Pentium III"
 Count the number of MMX instructions executed.
 An additional qualifier may be specified and comprises a list of
 the following keywords separated by
@@ -854,26 +917,30 @@ Count MMX unpack operation instructions.
 .Pp
 The default is to count all operations.
 .It Li p6-mmx-sat-instr-exec
-.Pq Tn "Pentium II" , Tn "Pentium III"
+.Pq Event B1H , Tn "Pentium II" , Tn "Pentium III"
 Count the number of MMX saturating instructions executed.
 .It Li p6-mmx-uops-exec
-.Pq Tn "Pentium II" , Tn "Pentium III"
+.Pq Event B2H , Tn "Pentium II" , Tn "Pentium III"
 Count the number of MMX micro-ops executed.
 .It Li p6-mul
+.Pq Event 12H
 Count the number of integer and floating-point multiplies, including
 speculative multiplies.
 This event is only allocated on counter 1.
 .It Li p6-partial-rat-stalls
+.Pq Event D2H
 Count the number of cycles or events for partial stalls.
 .It Li p6-resource-stalls
+.Pq Event A2H
 Count the number of cycles there was a resource related stall of any kind.
 .It Li p6-ret-seg-renames
-.Pq Tn "Pentium II" , Tn "Pentium III"
+.Pq Event D6H , Tn "Pentium II" , Tn "Pentium III"
 Count the number of segment register rename events retired.
 .It Li p6-sb-drains
+.Pq Event 04H
 Count the number of cycles the store buffer is draining.
 .It Li p6-seg-reg-renames Op Li ,umask= Ns Ar qualifier
-.Pq Tn "Pentium II" , Tn "Pentium III"
+.Pq Event D5H , Tn "Pentium II" , Tn "Pentium III"
 Count the number of segment register renames.
 An additional qualifier may be specified, and comprises a list of the
 following keywords separated by
@@ -893,7 +960,7 @@ Count renames for segment register GS.
 .Pp
 The default is to count operations affecting all segment registers.
 .It Li p6-seg-rename-stalls
-.Pq Tn "Pentium II" , Tn "Pentium III"
+.Pq Event D4H , Tn "Pentium II" , Tn "Pentium III"
 Count the number of segment register renaming stalls.
 An additional qualifier may be specified, and comprises a list of the
 following keywords separated by
@@ -913,8 +980,10 @@ Count stalls for segment register GS.
 .Pp
 The default is to count operations affecting all the segment registers.
 .It Li p6-segment-reg-loads
+.Pq Event 06H
 Count the number of segment register loads.
 .It Li p6-uops-retired
+.Pq Event C2H
 Count the number of micro-ops retired.
 .El
 .Ss Event Name Aliases