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authorian <ian@FreeBSD.org>2016-01-12 18:42:00 +0000
committerian <ian@FreeBSD.org>2016-01-12 18:42:00 +0000
commit33067117d569d0af9ff7609712f723ac6367820b (patch)
tree14739faaae386fb5d29687a3195d9a2dc44052f5 /lib
parent45b3c76b5591ca4e2553ff7090ef88f1a28a4700 (diff)
downloadFreeBSD-src-33067117d569d0af9ff7609712f723ac6367820b.zip
FreeBSD-src-33067117d569d0af9ff7609712f723ac6367820b.tar.gz
Restore uart PPS signal capture polarity to its historical norm, and add an
option to invert the polarity in software. Also add an option to capture very narrow pulses by using the hardware's MSR delta-bit capability of latching line state changes. This effectively reverts the mistake I made in r286595 which was based on empirical measurements made on hardware using TTL-level signaling, in which the logic levels are inverted from RS-232. Thus, this re-syncs the polarity with the requirements of RFC 2783, which is writen in terms of RS-232 signaling. Narrow-pulse mode uses the ability of most ns8250 and similar chips to provide a delta indication in the modem status register. The hardware is able to notice and latch the change when the pulse width is shorter than interrupt latency, which results in the signal no longer being asserted by time the interrupt service code runs. When running in this mode we get notified only that "a pulse happened" so the driver synthesizes both an ASSERT and a CLEAR event (with the same timestamp for each). When the pulse width is about equal to the interrupt latency the driver may intermittantly see both edges of the pulse. To prevent generating spurious events, the driver implements a half-second lockout period after generating an event before it will generate another. Differential Revision: https://reviews.freebsd.org/D4477
Diffstat (limited to 'lib')
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