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authoravg <avg@FreeBSD.org>2017-06-19 15:34:07 +0000
committeravg <avg@FreeBSD.org>2017-06-19 15:34:07 +0000
commitb411849ecdbddf7a09b3c2018a4f48eece59a672 (patch)
tree0d89b638d7dc07e923c98e0cfdbceec97525719d /lib/libpmc
parent01d96b2618b852fe2f740f536f56cd689fe8c375 (diff)
downloadFreeBSD-src-b411849ecdbddf7a09b3c2018a4f48eece59a672.zip
FreeBSD-src-b411849ecdbddf7a09b3c2018a4f48eece59a672.tar.gz
MFC r291494: Add support for Intel Skylake and Intel Broadwell PMC's.
Diffstat (limited to 'lib/libpmc')
-rw-r--r--lib/libpmc/libpmc.c118
1 files changed, 117 insertions, 1 deletions
diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c
index 2cdf6b7..e10e0f9 100644
--- a/lib/libpmc/libpmc.c
+++ b/lib/libpmc/libpmc.c
@@ -205,6 +205,20 @@ static const struct pmc_event_descr haswell_xeon_event_table[] =
__PMC_EV_ALIAS_HASWELL_XEON()
};
+static const struct pmc_event_descr broadwell_event_table[] =
+{
+ __PMC_EV_ALIAS_BROADWELL()
+};
+
+static const struct pmc_event_descr broadwell_xeon_event_table[] =
+{
+ __PMC_EV_ALIAS_BROADWELL_XEON()
+};
+
+static const struct pmc_event_descr skylake_event_table[] =
+{
+ __PMC_EV_ALIAS_SKYLAKE()
+};
static const struct pmc_event_descr ivybridge_event_table[] =
{
@@ -246,6 +260,11 @@ static const struct pmc_event_descr haswelluc_event_table[] =
__PMC_EV_ALIAS_HASWELLUC()
};
+static const struct pmc_event_descr broadwelluc_event_table[] =
+{
+ __PMC_EV_ALIAS_BROADWELLUC()
+};
+
static const struct pmc_event_descr sandybridgeuc_event_table[] =
{
__PMC_EV_ALIAS_SANDYBRIDGEUC()
@@ -274,6 +293,9 @@ PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CL
PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(broadwell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(broadwell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(skylake, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
@@ -320,6 +342,9 @@ PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell, iap);
+PMC_CLASS_TABLE_DESC(broadwell, IAP, broadwell, iap);
+PMC_CLASS_TABLE_DESC(broadwell_xeon, IAP, broadwell_xeon, iap);
+PMC_CLASS_TABLE_DESC(skylake, IAP, skylake, iap);
PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
@@ -329,6 +354,7 @@ PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap);
PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
+PMC_CLASS_TABLE_DESC(broadwelluc, UCP, broadwelluc, ucp);
PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
#endif
@@ -636,6 +662,12 @@ static struct pmc_event_alias core2_aliases_without_iaf[] = {
#define haswell_aliases_without_iaf core2_aliases_without_iaf
#define haswell_xeon_aliases core2_aliases
#define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf
+#define broadwell_aliases core2_aliases
+#define broadwell_aliases_without_iaf core2_aliases_without_iaf
+#define broadwell_xeon_aliases core2_aliases
+#define broadwell_xeon_aliases_without_iaf core2_aliases_without_iaf
+#define skylake_aliases core2_aliases
+#define skylake_aliases_without_iaf core2_aliases_without_iaf
#define ivybridge_aliases core2_aliases
#define ivybridge_aliases_without_iaf core2_aliases_without_iaf
#define ivybridge_xeon_aliases core2_aliases
@@ -796,6 +828,7 @@ static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = {
NULLMASK
};
+/* Broadwell is defined to use the same mask as Haswell */
static struct pmc_masks iap_rsp_mask_haswell[] = {
PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
@@ -811,6 +844,36 @@ static struct pmc_masks iap_rsp_mask_haswell[] = {
PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
+ /*
+ * For processor type 06_45H 22 is L4_HIT_LOCAL_L4
+ * and 23, 24 and 25 are also defined.
+ */
+ PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
+ PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
+ PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
+ PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
+ PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
+ PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
+ PMCMASK(RES_NON_DRAM, (1ULL << 37)),
+ NULLMASK
+};
+
+static struct pmc_masks iap_rsp_mask_skylake[] = {
+ PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
+ PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
+ PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
+ PMCMASK(REQ_PF_DATA_RD, (1ULL << 7)),
+ PMCMASK(REQ_PF_RFO, (1ULL << 8)),
+ PMCMASK(REQ_STRM_ST, (1ULL << 11)),
+ PMCMASK(REQ_OTHER, (1ULL << 15)),
+ PMCMASK(RES_ANY, (1ULL << 16)),
+ PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
+ PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
+ PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
+ PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
+ PMCMASK(RES_SUPPLIER_L4_HIT, (1ULL << 22)),
+ PMCMASK(RES_SUPPLIER_DRAM, (1ULL << 26)),
+ PMCMASK(RES_SUPPLIER_SPL_HIT, (1ULL << 30)),
PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
@@ -821,6 +884,7 @@ static struct pmc_masks iap_rsp_mask_haswell[] = {
NULLMASK
};
+
static int
iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
struct pmc_op_pmcallocate *pmc_config)
@@ -912,6 +976,20 @@ iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
} else
return (-1);
+ } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL ||
+ cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL_XEON) {
+ /* Broadwell is defined to use same mask as haswell */
+ if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
+ n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
+ } else
+ return (-1);
+
+ } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE) {
+ if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
+ n = pmc_parse_mask(iap_rsp_mask_skylake, p, &rsp);
+ } else
+ return (-1);
+
} else
return (-1);
@@ -2803,6 +2881,18 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
ev = haswell_xeon_event_table;
count = PMC_EVENT_TABLE_SIZE(haswell_xeon);
break;
+ case PMC_CPU_INTEL_BROADWELL:
+ ev = broadwell_event_table;
+ count = PMC_EVENT_TABLE_SIZE(broadwell);
+ break;
+ case PMC_CPU_INTEL_BROADWELL_XEON:
+ ev = broadwell_xeon_event_table;
+ count = PMC_EVENT_TABLE_SIZE(broadwell_xeon);
+ break;
+ case PMC_CPU_INTEL_SKYLAKE:
+ ev = skylake_event_table;
+ count = PMC_EVENT_TABLE_SIZE(skylake);
+ break;
case PMC_CPU_INTEL_IVYBRIDGE:
ev = ivybridge_event_table;
count = PMC_EVENT_TABLE_SIZE(ivybridge);
@@ -2848,6 +2938,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
ev = haswelluc_event_table;
count = PMC_EVENT_TABLE_SIZE(haswelluc);
break;
+ case PMC_CPU_INTEL_BROADWELL:
+ ev = broadwelluc_event_table;
+ count = PMC_EVENT_TABLE_SIZE(broadwelluc);
+ break;
case PMC_CPU_INTEL_SANDYBRIDGE:
ev = sandybridgeuc_event_table;
count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
@@ -3133,6 +3227,17 @@ pmc_init(void)
case PMC_CPU_INTEL_HASWELL_XEON:
PMC_MDEP_INIT_INTEL_V2(haswell_xeon);
break;
+ case PMC_CPU_INTEL_BROADWELL:
+ pmc_class_table[n++] = &ucf_class_table_descr;
+ pmc_class_table[n++] = &broadwelluc_class_table_descr;
+ PMC_MDEP_INIT_INTEL_V2(broadwell);
+ break;
+ case PMC_CPU_INTEL_BROADWELL_XEON:
+ PMC_MDEP_INIT_INTEL_V2(broadwell_xeon);
+ break;
+ case PMC_CPU_INTEL_SKYLAKE:
+ PMC_MDEP_INIT_INTEL_V2(skylake);
+ break;
case PMC_CPU_INTEL_IVYBRIDGE:
PMC_MDEP_INIT_INTEL_V2(ivybridge);
break;
@@ -3302,7 +3407,18 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
ev = haswell_xeon_event_table;
evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon);
break;
-
+ case PMC_CPU_INTEL_BROADWELL:
+ ev = broadwell_event_table;
+ evfence = broadwell_event_table + PMC_EVENT_TABLE_SIZE(broadwell);
+ break;
+ case PMC_CPU_INTEL_BROADWELL_XEON:
+ ev = broadwell_xeon_event_table;
+ evfence = broadwell_xeon_event_table + PMC_EVENT_TABLE_SIZE(broadwell_xeon);
+ break;
+ case PMC_CPU_INTEL_SKYLAKE:
+ ev = skylake_event_table;
+ evfence = skylake_event_table + PMC_EVENT_TABLE_SIZE(skylake);
+ break;
case PMC_CPU_INTEL_IVYBRIDGE:
ev = ivybridge_event_table;
evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
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