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author | gjb <gjb@FreeBSD.org> | 2012-02-25 14:31:25 +0000 |
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committer | gjb <gjb@FreeBSD.org> | 2012-02-25 14:31:25 +0000 |
commit | 9761e3fdaf71ba499c124e255c7d3648868e8fa0 (patch) | |
tree | 2b7318666575d98b59eff5fe1426e9b39f58d384 /lib/libpmc | |
parent | 07e034748ae7ddafecae472a77028d7132bf7e2d (diff) | |
download | FreeBSD-src-9761e3fdaf71ba499c124e255c7d3648868e8fa0.zip FreeBSD-src-9761e3fdaf71ba499c124e255c7d3648868e8fa0.tar.gz |
Fix various typos in manual pages.
Submitted by: amdmi3
PR: 165431
MFC after: 1 week
Diffstat (limited to 'lib/libpmc')
-rw-r--r-- | lib/libpmc/pmc.mips.3 | 4 | ||||
-rw-r--r-- | lib/libpmc/pmc.westmere.3 | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/lib/libpmc/pmc.mips.3 b/lib/libpmc/pmc.mips.3 index bad2046..2f9be21 100644 --- a/lib/libpmc/pmc.mips.3 +++ b/lib/libpmc/pmc.mips.3 @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd February 11, 2010 +.Dd February 25, 2012 .Dt PMC.MIPS 3 .Os .Sh NAME @@ -166,7 +166,7 @@ This includes all instructions that normally write to a general purpose register, but where the destination register was set to r0. .It Li INTEGER_MULDIV_COMPLETED .Pq Event 17, Counter 1 -Integer multipy and divide instructions completed. (MULxx, DIVx, MADDx, MSUBx). +Integer multiply and divide instructions completed. (MULxx, DIVx, MADDx, MSUBx). .It Li RF_STALL .Pq Event 18, Counter 0 Counts the total number of cycles where no instructions are issued diff --git a/lib/libpmc/pmc.westmere.3 b/lib/libpmc/pmc.westmere.3 index c5f1e1c..0b8934e 100644 --- a/lib/libpmc/pmc.westmere.3 +++ b/lib/libpmc/pmc.westmere.3 @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd March 24, 2010 +.Dd February 25, 2012 .Dt PMC.WESTMERE 3 .Os .Sh NAME @@ -643,7 +643,7 @@ Counter 0. .Pq Event 60H , Umask 08H Counts weighted cycles of offcore read requests of any kind. Include L2 prefetch requests. -Ccounter 0. +Counter 0. .It Li CACHE_LOCK_CYCLES.L1D_L2 .Pq Event 63H , Umask 01H Cycle count during which the L1D and L2 are locked. A lock is asserted when |