Remove superfluous paragraph macro.

5 files changed, 0 insertions, 5 deletions

diff --git a/lib/libpmc/pmc.3 b/lib/libpmc/pmc.3
index bceb9bd..0a537a5 100644
--- a/lib/libpmc/pmc.3
+++ b/lib/libpmc/pmc.3
@@ -225,7 +225,6 @@ CPUs.
 The timestamp counter on i386 and amd64 architecture CPUs.
 .El
 .Ss PMC Capabilities
-.Pp
 Capabilities of performance monitoring hardware are denoted using
 the
 .Vt "enum pmc_caps"
diff --git a/lib/libpmc/pmc.k7.3 b/lib/libpmc/pmc.k7.3
index 99fb964..59e6489 100644
--- a/lib/libpmc/pmc.k7.3
+++ b/lib/libpmc/pmc.k7.3
@@ -64,7 +64,6 @@ Each K7 CPU contains 4 PMCs with the following capabilities:
 .It PMC_CAP_WRITE Ta Yes
 .El
 .Ss Event Qualifiers
-.Pp
 Event specifiers for AMD K7 PMCs can have the following optional
 qualifiers:
 .Bl -tag -width indent
diff --git a/lib/libpmc/pmc.k8.3 b/lib/libpmc/pmc.k8.3
index 03c6bb6..e4eb081 100644
--- a/lib/libpmc/pmc.k8.3
+++ b/lib/libpmc/pmc.k8.3
@@ -67,7 +67,6 @@ Each CPU contains 4 PMCs with the following capabilities:
 .It PMC_CAP_WRITE Ta Yes
 .El
 .Ss Event Qualifiers
-.Pp
 Event specifiers for AMD K8 PMCs can have the following optional
 qualifiers:
 .Bl -tag -width indent
diff --git a/lib/libpmc/pmc.octeon.3 b/lib/libpmc/pmc.octeon.3
index e8851425..78638ba 100644
--- a/lib/libpmc/pmc.octeon.3
+++ b/lib/libpmc/pmc.octeon.3
@@ -36,7 +36,6 @@ family CPUs
 .Sh SYNOPSIS
 .In pmc.h
 .Sh DESCRIPTION
-.Pp
 There are two counters per core supported by the hardware and each is 64 bits
 wide.
 .Ss Event Specifiers (Programmable PMCs)
diff --git a/lib/libpmc/pmc.p4.3 b/lib/libpmc/pmc.p4.3
index 39df8e0..3d89fc1 100644
--- a/lib/libpmc/pmc.p4.3
+++ b/lib/libpmc/pmc.p4.3
@@ -90,7 +90,6 @@ These PMCs support the following capabilities:
 .It PMC_CAP_WRITE Ta Yes
 .El
 .Ss Event Qualifiers
-.Pp
 Event specifiers for Intel P4 PMCs can have the following common
 qualifiers:
 .Bl -tag -width indent