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author | jkoshy <jkoshy@FreeBSD.org> | 2008-12-08 12:28:48 +0000 |
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committer | jkoshy <jkoshy@FreeBSD.org> | 2008-12-08 12:28:48 +0000 |
commit | 672c135fef76269014512e62d821125bbcb042f5 (patch) | |
tree | 25a717439310a2cd220c525a2c79aeeeabfb80a6 /lib/libpmc | |
parent | 01085e085d51e1ee61dcba260fad1e95ee8a4e99 (diff) | |
download | FreeBSD-src-672c135fef76269014512e62d821125bbcb042f5.zip FreeBSD-src-672c135fef76269014512e62d821125bbcb042f5.tar.gz |
Document processor errata that affect performance measurement.
Diffstat (limited to 'lib/libpmc')
-rw-r--r-- | lib/libpmc/pmc.core.3 | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/lib/libpmc/pmc.core.3 b/lib/libpmc/pmc.core.3 index 55ef2e5..ce085ca 100644 --- a/lib/libpmc/pmc.core.3 +++ b/lib/libpmc/pmc.core.3 @@ -730,6 +730,58 @@ and the underlying hardware events used. .It Li interrupts Ta Li HW_Int_Rx .It Li unhalted-cycles Ta (unsupported) .El +.Sh PROCESSOR ERRATA +The following errata affect performance measurement on these +processors. +These errata are documented in +.Rs +.%T "Intel® CoreTM Duo Processor and Intel® CoreTM Solo Processor on 65 nm Process" +.%B "Specification Update" +.%N "Order Number 309222-017" +.%D July 2008 +.%Q "Intel Corporation" +.Re +.Bl -tag -width indent -compact +.It AE19 +Data prefetch performance monitoring events can only be enabled +on a single core. +.It AE25 +Performance monitoring counters that count external bus events +may report incorrect values after processor power state transitions. +.It AE28 +Performance monitoring events for retired floating point operations +(C1H) may not be accurate. +.It AE29 +DR3 address match on MOVD/MOVQ/MOVNTQ memory store +instruction may incorrectly increment performance monitoring count +for saturating simd instructions retired (Event CFH). +.It AE33 +Hardware prefetch performance monitoring events may be counted +inaccurately. +.It AE36 +The +.Li CPU_CLK_UNHALTED +performance monitoring event (Event 3CH) counts +clocks when the processor is in the C1/C2 processor power states. +.It AE39 +Certain performance monitoring counters related to bus, L2 cache +and power management are inaccurate. +.It AE51 +Performance monitoring events for retired instructions (Event C0H) may +not be accurate. +.It AE67 +Performance monitoring event +.Li FP_ASSIST +may not be accurate. +.It AE78 +Performance monitoring event for hardware prefetch requests (Event +4EH) and hardware prefetch request cache misses (Event 4FH) may not be +accurate. +.It AE82 +Performance monitoring event +.Li FP_MMX_TRANS_TO_MMX +may not count some transitions. +.El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , |