Aaron Daily of Adaptec has informed me that some form of paged SCB

algorithm is used on aic7770 Rev E or higher chips to improve perfomance.
This required a hardware change but we don't know exactly what (most
likely some special register to do fast SCB indexing into host memory),
and we are not at all sure that there are more than 4 SCBs on these
chips.  This probe will still classify the revision of the aic7xxx, but
we now default to 4 SCBs (at least until we know more of what was done).

This also fixes a bug in the timeout routine where we cleared a flag
too soon making it imposible to enter one section of the routine.

Submitted by: Timeout bug - Dan Eischen <deischen@iworks.InterWorks.org>

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