acpi_cpu: fixup for PIIX4E PCI config related to C2

This is triggered only if BIOS configures ACPI_BITREG_BUS_MASTER_RLD
aka BRLD_EN_BM to 1.
Rationale:
1. we do not support C3 on PIIX4E
2. bus master activity need not break out of C2 state
3. because of CPU_QUIRK_NO_BM_CTRL quirk we may reset bus master
   status which would result in immediate break out from C2

So if you have seen
cpu0: too many short sleeps, backing off to C1
with this chipset before you may want to try cx_lowest of C2 again.

Reviewed by: rpaulo (mentor), njl
Approved by: rpaulo (mentor)

0 files changed, 0 insertions, 0 deletions