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| author | eadler <eadler@FreeBSD.org> | 2014-02-04 03:36:42 +0000 |
|---|---|---|
| committer | eadler <eadler@FreeBSD.org> | 2014-02-04 03:36:42 +0000 |
| commit | ec294fd7f5fc5de11ed889d6c2d701f918d1ecfb (patch) | |
| tree | 7e76e370b9406b0383b17bd343084addb4ad6a25 /lib/libc/sparc64 | |
| parent | d374d7f398b846dc59d8a5ec3c7bfb318cf880af (diff) | |
| download | FreeBSD-src-ec294fd7f5fc5de11ed889d6c2d701f918d1ecfb.zip FreeBSD-src-ec294fd7f5fc5de11ed889d6c2d701f918d1ecfb.tar.gz | |
MFC r258779,r258780,r258787,r258822:
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
Similar to the (1 << 31) case it is not defined to do (2 << 30).
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Diffstat (limited to 'lib/libc/sparc64')
| -rw-r--r-- | lib/libc/sparc64/fpu/fpu.c | 6 | ||||
| -rw-r--r-- | lib/libc/sparc64/fpu/fpu_sqrt.c | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/lib/libc/sparc64/fpu/fpu.c b/lib/libc/sparc64/fpu/fpu.c index 4e92788..431207f 100644 --- a/lib/libc/sparc64/fpu/fpu.c +++ b/lib/libc/sparc64/fpu/fpu.c @@ -202,7 +202,7 @@ static const int opmask[] = {0, 0, 1, 3, 1}; * Implement a move operation for all supported operand types. The additional * nand and xor parameters will be applied to the upper 32 bit word of the * source operand. This allows to implement fabs and fneg (for fp operands - * only!) using this functions, too, by passing (1 << 31) for one of the + * only!) using this functions, too, by passing (1U << 31) for one of the * parameters, and 0 for the other. */ static void @@ -358,10 +358,10 @@ __fpu_execute(struct utrapframe *uf, struct fpemu *fe, u_int32_t insn, __fpu_mov(fe, type, rd, rs2, 0, 0); return (0); case FOP(INS2_FPop1, INSFP1_FNEG): - __fpu_mov(fe, type, rd, rs2, 0, (1 << 31)); + __fpu_mov(fe, type, rd, rs2, 0, (1U << 31)); return (0); case FOP(INS2_FPop1, INSFP1_FABS): - __fpu_mov(fe, type, rd, rs2, (1 << 31), 0); + __fpu_mov(fe, type, rd, rs2, (1U << 31), 0); return (0); case FOP(INS2_FPop1, INSFP1_FSQRT): __fpu_explode(fe, &fe->fe_f1, type, rs2); diff --git a/lib/libc/sparc64/fpu/fpu_sqrt.c b/lib/libc/sparc64/fpu/fpu_sqrt.c index 364384b..52290f2 100644 --- a/lib/libc/sparc64/fpu/fpu_sqrt.c +++ b/lib/libc/sparc64/fpu/fpu_sqrt.c @@ -257,7 +257,7 @@ __fpu_sqrt(fe) * double x correctly while doing the `known q=1.0'. * * We do this one mantissa-word at a time, as noted above, to - * save work. To avoid `(1 << 31) << 1', we also do the top bit + * save work. To avoid `(1U << 31) << 1', we also do the top bit * outside of each per-word loop. * * The calculation `t = y + bit' breaks down into `t0 = y0, ..., |
