Implement the AR933x interrupt driven UART code.

* Enable RX and host interrupts during bus probe/attach
* Disable all interrupts (+ host ISR) during bus detach
* Enable TX DONE interrupt only when we start transmitting; clear it when
  we're done.
* The RX/TX FIFO depth is still conjecture on my part.  I'll fix this
  shortly.
* The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty"
  interrupt.  Sigh.  So..
* .. in ar933x_bus_transmit(), wait for the FIFO to drain before
  continuing.

I dislike having to wait for the FIFO to drain, alas.

Tested:

* Atheros AP121 board, AR9331 SoC.

TODO:

* RX/TX overflow, RX error, BREAK support, etc.
* Figure out the true RX/TX FIFO depth.

0 files changed, 0 insertions, 0 deletions