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authorcognet <cognet@FreeBSD.org>2004-05-14 12:04:31 +0000
committercognet <cognet@FreeBSD.org>2004-05-14 12:04:31 +0000
commitbb6bbd6342ef3a05d837b89817ec6f058d1497b3 (patch)
tree6da949d33b96ce7f3985a2cbc32baeccf187c4d6 /lib/libc/arm/gen/setjmp.S
parent90f48ef1d2da8652d325e845334302aef9b6f5b9 (diff)
downloadFreeBSD-src-bb6bbd6342ef3a05d837b89817ec6f058d1497b3.zip
FreeBSD-src-bb6bbd6342ef3a05d837b89817ec6f058d1497b3.tar.gz
Import the FreeBSD/arm libc bits.
Obtained from: NetBSD
Diffstat (limited to 'lib/libc/arm/gen/setjmp.S')
-rw-r--r--lib/libc/arm/gen/setjmp.S132
1 files changed, 132 insertions, 0 deletions
diff --git a/lib/libc/arm/gen/setjmp.S b/lib/libc/arm/gen/setjmp.S
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+++ b/lib/libc/arm/gen/setjmp.S
@@ -0,0 +1,132 @@
+/* $NetBSD: setjmp.S,v 1.5 2003/04/05 23:08:51 bjh21 Exp $ */
+
+/*
+ * Copyright (c) 1997 Mark Brinicombe
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Mark Brinicombe
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/asm.h>
+__FBSDID("$FreeBSD$");
+/*
+ * C library -- setjmp, longjmp
+ *
+ * longjmp(a,v)
+ * will generate a "return(v)" from the last call to
+ * setjmp(a)
+ * by restoring registers from the stack.
+ * The previous signal state is restored.
+ */
+
+#define SOFTFLOAT /* XXX */
+ENTRY(setjmp)
+ /* Block all signals and retrieve the old signal mask */
+ stmfd sp!, {r0, r14}
+ mov r0, #0x00000000
+
+ bl PIC_SYM(_C_LABEL(sigblock), PLT)
+ mov r1, r0
+
+ ldmfd sp!, {r0, r14}
+
+ /* Store signal mask */
+ str r1, [r0, #(25 * 4)]
+
+ ldr r1, .Lsetjmp_magic
+ str r1, [r0], #4
+
+#ifdef SOFTFLOAT
+ add r0, r0, #52
+#else
+ /* Store fp registers */
+ sfm f4, 4, [r0], #48
+ /* Store fpsr */
+ rfs r1
+ str r1, [r0], #0x0004
+#endif /*SOFTFLOAT*/
+ /* Store integer registers */
+ stmia r0, {r4-r14}
+ mov r0, #0x00000000
+ mov r15, r14
+
+.Lsetjmp_magic:
+ .word _JB_MAGIC_SETJMP
+
+
+.weak _C_LABEL(longjmp)
+.set _C_LABEL(longjmp), _C_LABEL(__longjmp)
+ENTRY(__longjmp)
+ ldr r2, .Lsetjmp_magic
+ ldr r3, [r0]
+ teq r2, r3
+ bne botch
+
+ /* Fetch signal mask */
+ ldr r2, [r0, #(25 * 4)]
+
+ /* Set signal mask */
+ stmfd sp!, {r0, r1, r14}
+ sub sp, sp, #4 /* align the stack */
+
+ mov r0, r2
+ bl PIC_SYM(_C_LABEL(sigsetmask), PLT)
+
+ add sp, sp, #4 /* unalign the stack */
+ ldmfd sp!, {r0, r1, r14}
+
+ add r0, r0, #4
+#ifdef SOFTFLOAT
+ add r0, r0, #52
+#else
+ /* Restore fp registers */
+ lfm f4, 4, [r0], #48
+ /* Restore FPSR */
+ ldr r4, [r0], #0x0004
+ wfs r4
+#endif /* SOFTFLOAT */
+ /* Restore integer registers */
+ ldmia r0, {r4-r14}
+
+ /* Validate sp and r14 */
+ teq sp, #0
+ teqne r14, #0
+ beq botch
+
+ /* Set return value */
+
+ mov r0, r1
+ teq r0, #0x00000000
+ moveq r0, #0x00000001
+ mov r15, r14
+
+ /* validation failed, die die die. */
+botch:
+ bl PIC_SYM(_C_LABEL(longjmperror), PLT)
+ bl PIC_SYM(_C_LABEL(abort), PLT)
+ b . - 8 /* Cannot get here */
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