Update LLVM to r100520.

17 files changed, 406 insertions, 459 deletions

diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
index 734a545..0b64cb4 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
@@ -29,15 +29,18 @@ using namespace llvm;
 #include "X86GenAsmWriter.inc"
 #undef MachineInstr
 
-void X86ATTInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
+void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
+  printInstruction(MI, OS);
+}
 StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
   return getInstructionName(Opcode);
 }
 
 
-void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
+void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
+                                   raw_ostream &O) {
   switch (MI->getOperand(Op).getImm()) {
-  default: llvm_unreachable("Invalid ssecc argument!");
+  default: assert(0 && "Invalid ssecc argument!");
   case 0: O << "eq"; break;
   case 1: O << "lt"; break;
   case 2: O << "le"; break;
@@ -53,7 +56,8 @@ void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
 /// being encoded as a pc-relative value (e.g. for jumps and calls).  These
 /// print slightly differently than normal immediates.  For example, a $ is not
 /// emitted.
-void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
+void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
+                                        raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isImm())
     // Print this as a signed 32-bit value.
@@ -64,8 +68,8 @@ void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
   }
 }
 
-void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo) {
-  
+void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+                                     raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     O << '%' << getRegisterName(Op.getReg());
@@ -81,7 +85,8 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo) {
   }
 }
 
-void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
+void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op,
+                                             raw_ostream &O) {
   const MCOperand &BaseReg  = MI->getOperand(Op);
   const MCOperand &IndexReg = MI->getOperand(Op+2);
   const MCOperand &DispSpec = MI->getOperand(Op+3);
@@ -98,11 +103,11 @@ void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
   if (IndexReg.getReg() || BaseReg.getReg()) {
     O << '(';
     if (BaseReg.getReg())
-      printOperand(MI, Op);
+      printOperand(MI, Op, O);
     
     if (IndexReg.getReg()) {
       O << ',';
-      printOperand(MI, Op+2);
+      printOperand(MI, Op+2, O);
       unsigned ScaleVal = MI->getOperand(Op+1).getImm();
       if (ScaleVal != 1)
         O << ',' << ScaleVal;
@@ -111,11 +116,12 @@ void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
   }
 }
 
-void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op) {
+void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
+                                          raw_ostream &O) {
   // If this has a segment register, print it.
   if (MI->getOperand(Op+4).getReg()) {
-    printOperand(MI, Op+4);
+    printOperand(MI, Op+4, O);
     O << ':';
   }
-  printLeaMemReference(MI, Op);
+  printLeaMemReference(MI, Op, O);
 }
diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h
index d109a07..8d5d508 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h
+++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h
@@ -21,63 +21,62 @@ namespace llvm {
   
 class X86ATTInstPrinter : public MCInstPrinter {
 public:
-  X86ATTInstPrinter(raw_ostream &O, const MCAsmInfo &MAI)
-    : MCInstPrinter(O, MAI) {}
+  X86ATTInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {}
 
   
-  virtual void printInst(const MCInst *MI);
+  virtual void printInst(const MCInst *MI, raw_ostream &OS);
   virtual StringRef getOpcodeName(unsigned Opcode) const;
 
   // Autogenerated by tblgen.
-  void printInstruction(const MCInst *MI);
+  void printInstruction(const MCInst *MI, raw_ostream &OS);
   static const char *getRegisterName(unsigned RegNo);
   static const char *getInstructionName(unsigned Opcode);
 
-  void printOperand(const MCInst *MI, unsigned OpNo);
-  void printMemReference(const MCInst *MI, unsigned Op);
-  void printLeaMemReference(const MCInst *MI, unsigned Op);
-  void printSSECC(const MCInst *MI, unsigned Op);
-  void print_pcrel_imm(const MCInst *MI, unsigned OpNo);
+  void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
+  void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
+  void printLeaMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
+  void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
+  void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
   
-  void printopaquemem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
   
-  void printi8mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printi16mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printi32mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printi64mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printi128mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printf32mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printf64mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printf80mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printf128mem(const MCInst *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
+  void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printMemReference(MI, OpNo, O);
   }
-  void printlea32mem(const MCInst *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo);
+  void printlea32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printLeaMemReference(MI, OpNo, O);
   }
-  void printlea64mem(const MCInst *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo);
+  void printlea64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printLeaMemReference(MI, OpNo, O);
   }
-  void printlea64_32mem(const MCInst *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo);
+  void printlea64_32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+    printLeaMemReference(MI, OpNo, O);
   }
 };
   
diff --git a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
index 66bb914..f592396 100644
--- a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
@@ -36,7 +36,6 @@
 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/Mangler.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegistry.h"
@@ -47,7 +46,7 @@ using namespace llvm;
 // Primitive Helper Functions.
 //===----------------------------------------------------------------------===//
 
-void X86AsmPrinter::PrintPICBaseSymbol() const {
+void X86AsmPrinter::PrintPICBaseSymbol(raw_ostream &O) const {
   const TargetLowering *TLI = TM.getTargetLowering();
   O << *static_cast<const X86TargetLowering*>(TLI)->getPICBaseSymbol(MF,
                                                                     OutContext);
@@ -60,10 +59,11 @@ bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 
   if (Subtarget->isTargetCOFF()) {
     const Function *F = MF.getFunction();
-    O << "\t.def\t " << *CurrentFnSym << ";\t.scl\t" <<
-    (F->hasInternalLinkage() ? COFF::C_STAT : COFF::C_EXT)
-    << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT)
-    << ";\t.endef\n";
+    OutStreamer.EmitRawText("\t.def\t " + Twine(CurrentFnSym->getName()) +
+                            ";\t.scl\t" +
+                Twine(F->hasInternalLinkage() ? COFF::C_STAT : COFF::C_EXT) +
+                            ";\t.type\t" + Twine(COFF::DT_FCN << COFF::N_BTSHFT)
+                            + ";\t.endef");
   }
 
   // Have common code print out the function header with linkage info etc.
@@ -79,7 +79,8 @@ bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 /// printSymbolOperand - Print a raw symbol reference operand.  This handles
 /// jump tables, constant pools, global address and external symbols, all of
 /// which print to a label with various suffixes for relocation types etc.
-void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) {
+void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO,
+                                       raw_ostream &O) {
   switch (MO.getType()) {
   default: llvm_unreachable("unknown symbol type!");
   case MachineOperand::MO_JumpTableIndex:
@@ -87,7 +88,7 @@ void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) {
     break;
   case MachineOperand::MO_ConstantPoolIndex:
     O << *GetCPISymbol(MO.getIndex());
-    printOffset(MO.getOffset());
+    printOffset(MO.getOffset(), O);
     break;
   case MachineOperand::MO_GlobalAddress: {
     const GlobalValue *GV = MO.getGlobal();
@@ -136,7 +137,7 @@ void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) {
       O << *GVSym;
     else
       O << '(' << *GVSym << ')';
-    printOffset(MO.getOffset());
+    printOffset(MO.getOffset(), O);
     break;
   }
   case MachineOperand::MO_ExternalSymbol: {
@@ -182,14 +183,14 @@ void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) {
     break;
   case X86II::MO_GOT_ABSOLUTE_ADDRESS:
     O << " + [.-";
-    PrintPICBaseSymbol();
+    PrintPICBaseSymbol(O);
     O << ']';
     break;      
   case X86II::MO_PIC_BASE_OFFSET:
   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
     O << '-';
-    PrintPICBaseSymbol();
+    PrintPICBaseSymbol(O);
     break;
   case X86II::MO_TLSGD:     O << "@TLSGD";     break;
   case X86II::MO_GOTTPOFF:  O << "@GOTTPOFF";  break;
@@ -206,7 +207,8 @@ void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) {
 /// print_pcrel_imm - This is used to print an immediate value that ends up
 /// being encoded as a pc-relative value.  These print slightly differently, for
 /// example, a $ is not emitted.
-void X86AsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) {
+void X86AsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo,
+                                    raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(OpNo);
   switch (MO.getType()) {
   default: llvm_unreachable("Unknown pcrel immediate operand");
@@ -218,14 +220,14 @@ void X86AsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) {
     return;
   case MachineOperand::MO_GlobalAddress:
   case MachineOperand::MO_ExternalSymbol:
-    printSymbolOperand(MO);
+    printSymbolOperand(MO, O);
     return;
   }
 }
 
 
 void X86AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
-                                 const char *Modifier) {
+                                 raw_ostream &O, const char *Modifier) {
   const MachineOperand &MO = MI->getOperand(OpNo);
   switch (MO.getType()) {
   default: llvm_unreachable("unknown operand type!");
@@ -251,13 +253,14 @@ void X86AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
   case MachineOperand::MO_GlobalAddress: 
   case MachineOperand::MO_ExternalSymbol: {
     O << '$';
-    printSymbolOperand(MO);
+    printSymbolOperand(MO, O);
     break;
   }
   }
 }
 
-void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
+void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op,
+                               raw_ostream &O) {
   unsigned char value = MI->getOperand(Op).getImm();
   assert(value <= 7 && "Invalid ssecc argument!");
   switch (value) {
@@ -273,7 +276,7 @@ void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
 }
 
 void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
-                                         const char *Modifier) {
+                                         raw_ostream &O, const char *Modifier) {
   const MachineOperand &BaseReg  = MI->getOperand(Op);
   const MachineOperand &IndexReg = MI->getOperand(Op+2);
   const MachineOperand &DispSpec = MI->getOperand(Op+3);
@@ -294,7 +297,7 @@ void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
   } else {
     assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
            DispSpec.isJTI() || DispSpec.isSymbol());
-    printSymbolOperand(MI->getOperand(Op+3));
+    printSymbolOperand(MI->getOperand(Op+3), O);
   }
 
   if (HasParenPart) {
@@ -303,11 +306,11 @@ void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
 
     O << '(';
     if (HasBaseReg)
-      printOperand(MI, Op, Modifier);
+      printOperand(MI, Op, O, Modifier);
 
     if (IndexReg.getReg()) {
       O << ',';
-      printOperand(MI, Op+2, Modifier);
+      printOperand(MI, Op+2, O, Modifier);
       unsigned ScaleVal = MI->getOperand(Op+1).getImm();
       if (ScaleVal != 1)
         O << ',' << ScaleVal;
@@ -317,24 +320,26 @@ void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
 }
 
 void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
-                                      const char *Modifier) {
+                                      raw_ostream &O, const char *Modifier) {
   assert(isMem(MI, Op) && "Invalid memory reference!");
   const MachineOperand &Segment = MI->getOperand(Op+4);
   if (Segment.getReg()) {
-    printOperand(MI, Op+4, Modifier);
+    printOperand(MI, Op+4, O, Modifier);
     O << ':';
   }
-  printLeaMemReference(MI, Op, Modifier);
+  printLeaMemReference(MI, Op, O, Modifier);
 }
 
-void X86AsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
-  PrintPICBaseSymbol();
+void X86AsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op,
+                                  raw_ostream &O) {
+  PrintPICBaseSymbol(O);
   O << '\n';
-  PrintPICBaseSymbol();
+  PrintPICBaseSymbol(O);
   O << ':';
 }
 
-bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) {
+bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
+                                      raw_ostream &O) {
   unsigned Reg = MO.getReg();
   switch (Mode) {
   default: return true;  // Unknown mode.
@@ -363,7 +368,7 @@ bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) {
 ///
 bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                     unsigned AsmVariant,
-                                    const char *ExtraCode) {
+                                    const char *ExtraCode, raw_ostream &O) {
   // Does this asm operand have a single letter operand modifier?
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0) return true; // Unknown modifier.
@@ -378,12 +383,12 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
         return false;
       } 
       if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol()) {
-        printSymbolOperand(MO);
+        printSymbolOperand(MO, O);
         return false;
       }
       if (MO.isReg()) {
         O << '(';
-        printOperand(MI, OpNo);
+        printOperand(MI, OpNo, O);
         O << ')';
         return false;
       }
@@ -393,15 +398,15 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
       if (MO.isImm())
         O << MO.getImm();
       else if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol())
-        printSymbolOperand(MO);
+        printSymbolOperand(MO, O);
       else
-        printOperand(MI, OpNo);
+        printOperand(MI, OpNo, O);
       return false;
 
     case 'A': // Print '*' before a register (it must be a register)
       if (MO.isReg()) {
         O << '*';
-        printOperand(MI, OpNo);
+        printOperand(MI, OpNo, O);
         return false;
       }
       return true;
@@ -412,12 +417,12 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
     case 'k': // Print SImode register
     case 'q': // Print DImode register
       if (MO.isReg())
-        return printAsmMRegister(MO, ExtraCode[0]);
-      printOperand(MI, OpNo);
+        return printAsmMRegister(MO, ExtraCode[0], O);
+      printOperand(MI, OpNo, O);
       return false;
 
     case 'P': // This is the operand of a call, treat specially.
-      print_pcrel_imm(MI, OpNo);
+      print_pcrel_imm(MI, OpNo, O);
       return false;
 
     case 'n':  // Negate the immediate or print a '-' before the operand.
@@ -431,13 +436,14 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
     }
   }
 
-  printOperand(MI, OpNo);
+  printOperand(MI, OpNo, O);
   return false;
 }
 
 bool X86AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
                                           unsigned OpNo, unsigned AsmVariant,
-                                          const char *ExtraCode) {
+                                          const char *ExtraCode,
+                                          raw_ostream &O) {
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0) return true; // Unknown modifier.
 
@@ -451,11 +457,11 @@ bool X86AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
       // These only apply to registers, ignore on mem.
       break;
     case 'P': // Don't print @PLT, but do print as memory.
-      printMemReference(MI, OpNo, "no-rip");
+      printMemReference(MI, OpNo, O, "no-rip");
       return false;
     }
   }
-  printMemReference(MI, OpNo);
+  printMemReference(MI, OpNo, O);
   return false;
 }
 
@@ -570,10 +576,11 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
     // Emit type information for external functions
     for (X86COFFMachineModuleInfo::stub_iterator I = COFFMMI.stub_begin(),
            E = COFFMMI.stub_end(); I != E; ++I) {
-      O << "\t.def\t " << I->getKeyData()
-        << ";\t.scl\t" << COFF::C_EXT
-        << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT)
-        << ";\t.endef\n";
+      OutStreamer.EmitRawText("\t.def\t " + Twine(I->getKeyData()) +
+                              ";\t.scl\t" + Twine(COFF::C_EXT) +
+                              ";\t.type\t" +
+                              Twine(COFF::DT_FCN << COFF::N_BTSHFT) +
+                              ";\t.endef");
     }
 
     if (Subtarget->isTargetCygMing()) {
@@ -598,10 +605,13 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
                                                           true,
                                                    SectionKind::getMetadata()));
         for (unsigned i = 0, e = DLLExportedGlobals.size(); i != e; ++i)
-          O << "\t.ascii \" -export:" << *DLLExportedGlobals[i] << ",data\"\n";
+          OutStreamer.EmitRawText("\t.ascii \" -export:" +
+                                  Twine(DLLExportedGlobals[i]->getName()) +
+                                  ",data\"");
 
         for (unsigned i = 0, e = DLLExportedFns.size(); i != e; ++i)
-          O << "\t.ascii \" -export:" << *DLLExportedFns[i] << "\"\n";
+          OutStreamer.EmitRawText("\t.ascii \" -export:" +
+                                  Twine(DLLExportedFns[i]->getName()) + "\"");
       }
     }
   }
@@ -618,12 +628,11 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
       OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
       const TargetData *TD = TM.getTargetData();
 
-      for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
-        O << *Stubs[i].first << ":\n"
-          << (TD->getPointerSize() == 8 ?
-              MAI->getData64bitsDirective() : MAI->getData32bitsDirective())
-          << *Stubs[i].second.getPointer() << '\n';
-
+      for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
+        OutStreamer.EmitLabel(Stubs[i].first);
+        OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
+                                    TD->getPointerSize(), 0);
+      }
       Stubs.clear();
     }
   }
@@ -636,12 +645,11 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
 
 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
                                              unsigned SyntaxVariant,
-                                             const MCAsmInfo &MAI,
-                                             raw_ostream &O) {
+                                             const MCAsmInfo &MAI) {
   if (SyntaxVariant == 0)
-    return new X86ATTInstPrinter(O, MAI);
+    return new X86ATTInstPrinter(MAI);
   if (SyntaxVariant == 1)
-    return new X86IntelInstPrinter(O, MAI);
+    return new X86IntelInstPrinter(MAI);
   return 0;
 }
 
diff --git a/lib/Target/X86/AsmPrinter/X86AsmPrinter.h b/lib/Target/X86/AsmPrinter/X86AsmPrinter.h
index 28c25f9..ee59289 100644
--- a/lib/Target/X86/AsmPrinter/X86AsmPrinter.h
+++ b/lib/Target/X86/AsmPrinter/X86AsmPrinter.h
@@ -19,7 +19,6 @@
 #include "../X86TargetMachine.h"
 #include "llvm/ADT/StringSet.h"
 #include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/DwarfWriter.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Support/Compiler.h"
@@ -35,9 +34,8 @@ class MCSymbol;
 class VISIBILITY_HIDDEN X86AsmPrinter : public AsmPrinter {
   const X86Subtarget *Subtarget;
  public:
-  explicit X86AsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
-                         MCStreamer &Streamer)
-    : AsmPrinter(O, TM, Streamer) {
+  explicit X86AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
+    : AsmPrinter(TM, Streamer) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }
 
@@ -47,85 +45,41 @@ class VISIBILITY_HIDDEN X86AsmPrinter : public AsmPrinter {
   
   const X86Subtarget &getSubtarget() const { return *Subtarget; }
 
-  void getAnalysisUsage(AnalysisUsage &AU) const {
-    AU.setPreservesAll();
-    AU.addRequired<MachineModuleInfo>();
-    AU.addRequired<DwarfWriter>();
-    AsmPrinter::getAnalysisUsage(AU);
-  }
-
   virtual void EmitStartOfAsmFile(Module &M);
 
   virtual void EmitEndOfAsmFile(Module &M);
   
   virtual void EmitInstruction(const MachineInstr *MI);
   
-  void printSymbolOperand(const MachineOperand &MO);
+  void printSymbolOperand(const MachineOperand &MO, raw_ostream &O);
 
   // These methods are used by the tablegen'erated instruction printer.
-  void printOperand(const MachineInstr *MI, unsigned OpNo,
+  void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O,
                     const char *Modifier = 0);
-  void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo);
-
-  void printopaquemem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-
-  void printi8mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printi16mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printi32mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printi64mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printi128mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printf32mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printf64mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printf80mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printf128mem(const MachineInstr *MI, unsigned OpNo) {
-    printMemReference(MI, OpNo);
-  }
-  void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo);
-  }
-  void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo);
-  }
-  void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
-    printLeaMemReference(MI, OpNo, "subreg64");
-  }
+  void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
 
-  bool printAsmMRegister(const MachineOperand &MO, char Mode);
+  bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
-                       unsigned AsmVariant, const char *ExtraCode);
+                       unsigned AsmVariant, const char *ExtraCode,
+                       raw_ostream &OS);
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
-                             unsigned AsmVariant, const char *ExtraCode);
+                             unsigned AsmVariant, const char *ExtraCode,
+                             raw_ostream &OS);
 
   void printMachineInstruction(const MachineInstr *MI);
-  void printSSECC(const MachineInstr *MI, unsigned Op);
-  void printMemReference(const MachineInstr *MI, unsigned Op,
+  void printSSECC(const MachineInstr *MI, unsigned Op, raw_ostream &O);
+  void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
                          const char *Modifier=NULL);
-  void printLeaMemReference(const MachineInstr *MI, unsigned Op,
+  void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
                             const char *Modifier=NULL);
 
-  void printPICLabel(const MachineInstr *MI, unsigned Op);
+  void printPICLabel(const MachineInstr *MI, unsigned Op, raw_ostream &O);
 
-  void PrintPICBaseSymbol() const;
+  void PrintPICBaseSymbol(raw_ostream &O) const;
   
   bool runOnMachineFunction(MachineFunction &F);
+  
+  void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
 };
 
 } // end namespace llvm
diff --git a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp
index 610beb5..7e0a9bb 100644
--- a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp
@@ -28,14 +28,17 @@ using namespace llvm;
 #include "X86GenAsmWriter1.inc"
 #undef MachineInstr
 
-void X86IntelInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
+void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
+  printInstruction(MI, OS);
+}
 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
   return getInstructionName(Opcode);
 }
 
-void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
+void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
+                                     raw_ostream &O) {
   switch (MI->getOperand(Op).getImm()) {
-  default: llvm_unreachable("Invalid ssecc argument!");
+  default: assert(0 && "Invalid ssecc argument!");
   case 0: O << "eq"; break;
   case 1: O << "lt"; break;
   case 2: O << "le"; break;
@@ -49,7 +52,8 @@ void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
 
 /// print_pcrel_imm - This is used to print an immediate value that ends up
 /// being encoded as a pc-relative value.
-void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
+void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
+                                          raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isImm())
     O << Op.getImm();
@@ -65,9 +69,7 @@ static void PrintRegName(raw_ostream &O, StringRef RegName) {
 }
 
 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
-                                     const char *Modifier) {
-  assert(Modifier == 0 && "Modifiers should not be used");
-  
+                                       raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     PrintRegName(O, getRegisterName(Op.getReg()));
@@ -79,7 +81,8 @@ void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   }
 }
 
-void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
+void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op,
+                                               raw_ostream &O) {
   const MCOperand &BaseReg  = MI->getOperand(Op);
   unsigned ScaleVal         = MI->getOperand(Op+1).getImm();
   const MCOperand &IndexReg = MI->getOperand(Op+2);
@@ -89,7 +92,7 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
   
   bool NeedPlus = false;
   if (BaseReg.getReg()) {
-    printOperand(MI, Op);
+    printOperand(MI, Op, O);
     NeedPlus = true;
   }
   
@@ -97,7 +100,7 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
     if (NeedPlus) O << " + ";
     if (ScaleVal != 1)
       O << ScaleVal << '*';
-    printOperand(MI, Op+2);
+    printOperand(MI, Op+2, O);
     NeedPlus = true;
   }
   
@@ -124,11 +127,12 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
   O << ']';
 }
 
-void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op) {
+void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
+                                            raw_ostream &O) {
   // If this has a segment register, print it.
   if (MI->getOperand(Op+4).getReg()) {
-    printOperand(MI, Op+4);
+    printOperand(MI, Op+4, O);
     O << ':';
   }
-  printLeaMemReference(MI, Op);
+  printLeaMemReference(MI, Op, O);
 }
diff --git a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h
index 545bf84..a0beeb2 100644
--- a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h
+++ b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h
@@ -22,77 +22,76 @@ namespace llvm {
   
 class X86IntelInstPrinter : public MCInstPrinter {
 public:
-  X86IntelInstPrinter(raw_ostream &O, const MCAsmInfo &MAI)
-    : MCInstPrinter(O, MAI) {}
+  X86IntelInstPrinter(const MCAsmInfo &MAI)
+    : MCInstPrinter(MAI) {}
   
-  virtual void printInst(const MCInst *MI);
+  virtual void printInst(const MCInst *MI, raw_ostream &OS);
   virtual StringRef getOpcodeName(unsigned Opcode) const;
   
   // Autogenerated by tblgen.
-  void printInstruction(const MCInst *MI);
+  void printInstruction(const MCInst *MI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
   static const char *getInstructionName(unsigned Opcode);
 
 
-  void printOperand(const MCInst *MI, unsigned OpNo,
-                    const char *Modifier = 0);
-  void printMemReference(const MCInst *MI, unsigned Op);
-  void printLeaMemReference(const MCInst *MI, unsigned Op);
-  void printSSECC(const MCInst *MI, unsigned Op);
-  void print_pcrel_imm(const MCInst *MI, unsigned OpNo);
+  void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
+  void printLeaMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
+  void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
+  void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   
-  void printopaquemem(const MCInst *MI, unsigned OpNo) {
+  void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "OPAQUE PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
   
-  void printi8mem(const MCInst *MI, unsigned OpNo) {
+  void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "BYTE PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printi16mem(const MCInst *MI, unsigned OpNo) {
+  void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "WORD PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printi32mem(const MCInst *MI, unsigned OpNo) {
+  void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "DWORD PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printi64mem(const MCInst *MI, unsigned OpNo) {
+  void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "QWORD PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printi128mem(const MCInst *MI, unsigned OpNo) {
+  void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "XMMWORD PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printf32mem(const MCInst *MI, unsigned OpNo) {
+  void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "DWORD PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printf64mem(const MCInst *MI, unsigned OpNo) {
+  void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "QWORD PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printf80mem(const MCInst *MI, unsigned OpNo) {
+  void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "XWORD PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printf128mem(const MCInst *MI, unsigned OpNo) {
+  void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "XMMWORD PTR ";
-    printMemReference(MI, OpNo);
+    printMemReference(MI, OpNo, O);
   }
-  void printlea32mem(const MCInst *MI, unsigned OpNo) {
+  void printlea32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "DWORD PTR ";
-    printLeaMemReference(MI, OpNo);
+    printLeaMemReference(MI, OpNo, O);
   }
-  void printlea64mem(const MCInst *MI, unsigned OpNo) {
+  void printlea64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "QWORD PTR ";
-    printLeaMemReference(MI, OpNo);
+    printLeaMemReference(MI, OpNo, O);
   }
-  void printlea64_32mem(const MCInst *MI, unsigned OpNo) {
+  void printlea64_32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
     O << "QWORD PTR ";
-    printLeaMemReference(MI, OpNo);
+    printLeaMemReference(MI, OpNo, O);
   }
 };
   
diff --git a/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp b/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
index c851ca3..a290eb0 100644
--- a/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
+++ b/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
@@ -326,70 +326,76 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   }
 }
 
+void X86AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
+                                           raw_ostream &O) {
+  // FIXME: if this is implemented for another target before it goes
+  // away completely, the common part should be moved into AsmPrinter.
+  O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
+  unsigned NOps = MI->getNumOperands();
+  // cast away const; DIetc do not take const operands for some reason.
+  DIVariable V((MDNode*)(MI->getOperand(NOps-1).getMetadata()));
+  O << V.getName();
+  O << " <- ";
+  if (NOps==3) {
+    // Register or immediate value. Register 0 means undef.
+    assert(MI->getOperand(0).isReg() ||
+           MI->getOperand(0).isImm() ||
+           MI->getOperand(0).isFPImm());
+    if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == 0) {
+      // Suppress offset in this case, it is not meaningful.
+      O << "undef";
+      OutStreamer.AddBlankLine();
+      return;
+    }
+    
+    if (MI->getOperand(0).isFPImm()) {
+      // This is more naturally done in printOperand, but since the only use
+      // of such an operand is in this comment and that is temporary (and it's
+      // ugly), we prefer to keep this localized.
+      // The include of Type.h may be removable when this code is.
+      if (MI->getOperand(0).getFPImm()->getType()->isFloatTy() ||
+          MI->getOperand(0).getFPImm()->getType()->isDoubleTy())
+        MI->getOperand(0).print(O, &TM);
+      else {
+        // There is no good way to print long double.  Convert a copy to
+        // double.  Ah well, it's only a comment.
+        bool ignored;
+        APFloat APF = APFloat(MI->getOperand(0).getFPImm()->getValueAPF());
+        APF.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
+                    &ignored);
+        O << "(long double) " << APF.convertToDouble();
+      }
+    } else
+      printOperand(MI, 0, O);
+  } else {
+    if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == 0) {
+      // Suppress offset in this case, it is not meaningful.
+      O << "undef";
+      OutStreamer.AddBlankLine();
+      return;
+    }
+    // Frame address.  Currently handles register +- offset only.
+    assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm());
+    O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O);
+    O << ']';
+  }
+  O << "+";
+  printOperand(MI, NOps-2, O);
+}
 
 
 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
   X86MCInstLower MCInstLowering(OutContext, Mang, *this);
   switch (MI->getOpcode()) {
-  case TargetOpcode::DBG_VALUE: {
-    // FIXME: if this is implemented for another target before it goes
-    // away completely, the common part should be moved into AsmPrinter.
-    if (!VerboseAsm)
-      return;
-    O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
-    unsigned NOps = MI->getNumOperands();
-    // cast away const; DIetc do not take const operands for some reason.
-    DIVariable V((MDNode*)(MI->getOperand(NOps-1).getMetadata()));
-    O << V.getName();
-    O << " <- ";
-    if (NOps==3) {
-      // Register or immediate value. Register 0 means undef.
-      assert(MI->getOperand(0).getType()==MachineOperand::MO_Register ||
-             MI->getOperand(0).getType()==MachineOperand::MO_Immediate ||
-             MI->getOperand(0).getType()==MachineOperand::MO_FPImmediate);
-      if (MI->getOperand(0).getType()==MachineOperand::MO_Register &&
-          MI->getOperand(0).getReg()==0) {
-        // Suppress offset in this case, it is not meaningful.
-        O << "undef";
-        OutStreamer.AddBlankLine();
-        return;
-      } else if (MI->getOperand(0).getType()==MachineOperand::MO_FPImmediate) {
-        // This is more naturally done in printOperand, but since the only use
-        // of such an operand is in this comment and that is temporary (and it's
-        // ugly), we prefer to keep this localized.
-        // The include of Type.h may be removable when this code is.
-        if (MI->getOperand(0).getFPImm()->getType()->isFloatTy() ||
-            MI->getOperand(0).getFPImm()->getType()->isDoubleTy())
-          MI->getOperand(0).print(O, &TM);
-        else {
-          // There is no good way to print long double.  Convert a copy to
-          // double.  Ah well, it's only a comment.
-          bool ignored;
-          APFloat APF = APFloat(MI->getOperand(0).getFPImm()->getValueAPF());
-          APF.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
-                      &ignored);
-          O << "(long double) " << APF.convertToDouble();
-        }
-      } else
-        printOperand(MI, 0);
-    } else {
-      if (MI->getOperand(0).getType()==MachineOperand::MO_Register &&
-          MI->getOperand(0).getReg()==0) {
-        // Suppress offset in this case, it is not meaningful.
-        O << "undef";
-        OutStreamer.AddBlankLine();
-        return;
-      }
-      // Frame address.  Currently handles register +- offset only.
-      assert(MI->getOperand(0).getType()==MachineOperand::MO_Register);
-      assert(MI->getOperand(3).getType()==MachineOperand::MO_Immediate);
-      O << '['; printOperand(MI, 0); O << '+'; printOperand(MI, 3); O << ']';
+  case TargetOpcode::DBG_VALUE:
+    if (isVerbose() && OutStreamer.hasRawTextSupport()) {
+      std::string TmpStr;
+      raw_string_ostream OS(TmpStr);
+      PrintDebugValueComment(MI, OS);
+      OutStreamer.EmitRawText(StringRef(OS.str()));
     }
-    O << "+";
-    printOperand(MI, NOps-2);
-    OutStreamer.AddBlankLine();
     return;
-  }
+      
   case X86::MOVPC32r: {
     MCInst TmpInst;
     // This is a pseudo op for a two instruction sequence with a label, which
diff --git a/lib/Target/X86/SSEDomainFix.cpp b/lib/Target/X86/SSEDomainFix.cpp
index 395ab57..4b54676 100644
--- a/lib/Target/X86/SSEDomainFix.cpp
+++ b/lib/Target/X86/SSEDomainFix.cpp
@@ -23,49 +23,11 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/Support/Allocator.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
-namespace {
-
-/// Allocate objects from a pool, allow objects to be recycled, and provide a
-/// way of deleting everything.
-template<typename T, unsigned PageSize = 64>
-class PoolAllocator {
-  std::vector<T*> Pages, Avail;
-public:
-  ~PoolAllocator() { Clear(); }
-
-  T* Alloc() {
-    if (Avail.empty()) {
-      T *p = new T[PageSize];
-      Pages.push_back(p);
-      Avail.reserve(PageSize);
-      for (unsigned n = 0; n != PageSize; ++n)
-        Avail.push_back(p+n);
-    }
-    T *p = Avail.back();
-    Avail.pop_back();
-    return p;
-  }
-
-  // Allow object to be reallocated. It won't be reconstructed.
-  void Recycle(T *p) {
-    p->clear();
-    Avail.push_back(p);
-  }
-
-  // Destroy all objects, make sure there are no external pointers to them.
-  void Clear() {
-    Avail.clear();
-    while (!Pages.empty()) {
-      delete[] Pages.back();
-      Pages.pop_back();
-    }
-  }
-};
-
 /// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
 /// of execution domains.
 ///
@@ -81,14 +43,15 @@ public:
 /// domain, but if we were forced to pay the penalty of a domain crossing, we
 /// keep track of the fact the the register is now available in multiple
 /// domains.
+namespace {
 struct DomainValue {
   // Basic reference counting.
   unsigned Refs;
 
-  // Available domains. For an open DomainValue, it is the still possible
-  // domains for collapsing. For a collapsed DomainValue it is the domains where
-  // the register is available for free.
-  unsigned Mask;
+  // Bitmask of available domains. For an open DomainValue, it is the still
+  // possible domains for collapsing. For a collapsed DomainValue it is the
+  // domains where the register is available for free.
+  unsigned AvailableDomains;
 
   // Position of the last defining instruction.
   unsigned Dist;
@@ -96,38 +59,51 @@ struct DomainValue {
   // Twiddleable instructions using or defining these registers.
   SmallVector<MachineInstr*, 8> Instrs;
 
-  // Collapsed DomainValue have no instructions to twiddle - it simply keeps
+  // A collapsed DomainValue has no instructions to twiddle - it simply keeps
   // track of the domains where the registers are already available.
-  bool collapsed() const { return Instrs.empty(); }
+  bool isCollapsed() const { return Instrs.empty(); }
 
-  // Is any domain in mask available?
-  bool compat(unsigned mask) const {
-    return Mask & mask;
+  // Is domain available?
+  bool hasDomain(unsigned domain) const {
+    return AvailableDomains & (1u << domain);
   }
 
   // Mark domain as available.
-  void add(unsigned domain) {
-    Mask |= 1u << domain;
+  void addDomain(unsigned domain) {
+    AvailableDomains |= 1u << domain;
+  }
+
+  // Restrict to a single domain available.
+  void setSingleDomain(unsigned domain) {
+    AvailableDomains = 1u << domain;
+  }
+
+  // Return bitmask of domains that are available and in mask.
+  unsigned getCommonDomains(unsigned mask) const {
+    return AvailableDomains & mask;
   }
 
-  // First domain available in mask.
-  unsigned firstDomain() const {
-    return CountTrailingZeros_32(Mask);
+  // First domain available.
+  unsigned getFirstDomain() const {
+    return CountTrailingZeros_32(AvailableDomains);
   }
 
   DomainValue() { clear(); }
 
   void clear() {
-    Refs = Mask = Dist = 0;
+    Refs = AvailableDomains = Dist = 0;
     Instrs.clear();
   }
 };
+}
 
 static const unsigned NumRegs = 16;
 
+namespace {
 class SSEDomainFixPass : public MachineFunctionPass {
   static char ID;
-  PoolAllocator<DomainValue> Pool;
+  SpecificBumpPtrAllocator<DomainValue> Allocator;
+  SmallVector<DomainValue*,16> Avail;
 
   MachineFunction *MF;
   const X86InstrInfo *TII;
@@ -156,6 +132,10 @@ private:
   // Register mapping.
   int RegIndex(unsigned Reg);
 
+  // DomainValue allocation.
+  DomainValue *Alloc(int domain = -1);
+  void Recycle(DomainValue*);
+
   // LiveRegs manipulations.
   void SetLiveReg(int rx, DomainValue *DV);
   void Kill(int rx);
@@ -182,17 +162,35 @@ int SSEDomainFixPass::RegIndex(unsigned reg) {
   return reg < NumRegs ? reg : -1;
 }
 
+DomainValue *SSEDomainFixPass::Alloc(int domain) {
+  DomainValue *dv = Avail.empty() ?
+                      new(Allocator.Allocate()) DomainValue :
+                      Avail.pop_back_val();
+  dv->Dist = Distance;
+  if (domain >= 0)
+    dv->addDomain(domain);
+  return dv;
+}
+
+void SSEDomainFixPass::Recycle(DomainValue *dv) {
+  assert(dv && "Cannot recycle NULL");
+  dv->clear();
+  Avail.push_back(dv);
+}
+
 /// Set LiveRegs[rx] = dv, updating reference counts.
 void SSEDomainFixPass::SetLiveReg(int rx, DomainValue *dv) {
   assert(unsigned(rx) < NumRegs && "Invalid index");
-  if (!LiveRegs)
-    LiveRegs = (DomainValue**)calloc(sizeof(DomainValue*), NumRegs);
+  if (!LiveRegs) {
+    LiveRegs = new DomainValue*[NumRegs];
+    std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0);
+  }
 
   if (LiveRegs[rx] == dv)
     return;
   if (LiveRegs[rx]) {
     assert(LiveRegs[rx]->Refs && "Bad refcount");
-    if (--LiveRegs[rx]->Refs == 0) Pool.Recycle(LiveRegs[rx]);
+    if (--LiveRegs[rx]->Refs == 0) Recycle(LiveRegs[rx]);
   }
   LiveRegs[rx] = dv;
   if (dv) ++dv->Refs;
@@ -205,8 +203,8 @@ void SSEDomainFixPass::Kill(int rx) {
 
   // Before killing the last reference to an open DomainValue, collapse it to
   // the first available domain.
-  if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->collapsed())
-    Collapse(LiveRegs[rx], LiveRegs[rx]->firstDomain());
+  if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->isCollapsed())
+    Collapse(LiveRegs[rx], LiveRegs[rx]->getFirstDomain());
   else
     SetLiveReg(rx, 0);
 }
@@ -216,54 +214,45 @@ void SSEDomainFixPass::Force(int rx, unsigned domain) {
   assert(unsigned(rx) < NumRegs && "Invalid index");
   DomainValue *dv;
   if (LiveRegs && (dv = LiveRegs[rx])) {
-    if (dv->collapsed())
-      dv->add(domain);
+    if (dv->isCollapsed())
+      dv->addDomain(domain);
     else
       Collapse(dv, domain);
   } else {
     // Set up basic collapsed DomainValue.
-    dv = Pool.Alloc();
-    dv->Dist = Distance;
-    dv->add(domain);
-    SetLiveReg(rx, dv);
+    SetLiveReg(rx, Alloc(domain));
   }
 }
 
 /// Collapse open DomainValue into given domain. If there are multiple
 /// registers using dv, they each get a unique collapsed DomainValue.
 void SSEDomainFixPass::Collapse(DomainValue *dv, unsigned domain) {
-  assert(dv->compat(1u << domain) && "Cannot collapse");
+  assert(dv->hasDomain(domain) && "Cannot collapse");
 
   // Collapse all the instructions.
-  while (!dv->Instrs.empty()) {
-    MachineInstr *mi = dv->Instrs.back();
-    TII->SetSSEDomain(mi, domain);
-    dv->Instrs.pop_back();
-  }
-  dv->Mask = 1u << domain;
+  while (!dv->Instrs.empty())
+    TII->SetSSEDomain(dv->Instrs.pop_back_val(), domain);
+  dv->setSingleDomain(domain);
 
   // If there are multiple users, give them new, unique DomainValues.
-  if (LiveRegs && dv->Refs > 1) {
+  if (LiveRegs && dv->Refs > 1)
     for (unsigned rx = 0; rx != NumRegs; ++rx)
-      if (LiveRegs[rx] == dv) {
-        DomainValue *dv2 = Pool.Alloc();
-        dv2->Dist = Distance;
-        dv2->add(domain);
-        SetLiveReg(rx, dv2);
-      }
-  }
+      if (LiveRegs[rx] == dv)
+        SetLiveReg(rx, Alloc(domain));
 }
 
 /// Merge - All instructions and registers in B are moved to A, and B is
 /// released.
 bool SSEDomainFixPass::Merge(DomainValue *A, DomainValue *B) {
-  assert(!A->collapsed() && "Cannot merge into collapsed");
-  assert(!B->collapsed() && "Cannot merge from collapsed");
+  assert(!A->isCollapsed() && "Cannot merge into collapsed");
+  assert(!B->isCollapsed() && "Cannot merge from collapsed");
   if (A == B)
     return true;
-  if (!A->compat(B->Mask))
+  // Restrict to the domains that A and B have in common.
+  unsigned common = A->getCommonDomains(B->AvailableDomains);
+  if (!common)
     return false;
-  A->Mask &= B->Mask;
+  A->AvailableDomains = common;
   A->Dist = std::max(A->Dist, B->Dist);
   A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
   for (unsigned rx = 0; rx != NumRegs; ++rx)
@@ -290,18 +279,18 @@ void SSEDomainFixPass::enterBasicBlock() {
       }
 
       // We have a live DomainValue from more than one predecessor.
-      if (LiveRegs[rx]->collapsed()) {
+      if (LiveRegs[rx]->isCollapsed()) {
         // We are already collapsed, but predecessor is not. Force him.
-        if (!pdv->collapsed())
-          Collapse(pdv, LiveRegs[rx]->firstDomain());
+        if (!pdv->isCollapsed())
+          Collapse(pdv, LiveRegs[rx]->getFirstDomain());
         continue;
       }
-      
+
       // Currently open, merge in predecessor.
-      if (!pdv->collapsed())
+      if (!pdv->isCollapsed())
         Merge(LiveRegs[rx], pdv);
       else
-        Collapse(LiveRegs[rx], pdv->firstDomain());
+        Collapse(LiveRegs[rx], pdv->getFirstDomain());
     }
   }
 }
@@ -332,8 +321,11 @@ void SSEDomainFixPass::visitHardInstr(MachineInstr *mi, unsigned domain) {
 
 // A soft instruction can be changed to work in other domains given by mask.
 void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) {
+  // Bitmask of available domains for this instruction after taking collapsed
+  // operands into account.
+  unsigned available = mask;
+
   // Scan the explicit use operands for incoming domains.
-  unsigned collmask = mask;
   SmallVector<int, 4> used;
   if (LiveRegs)
     for (unsigned i = mi->getDesc().getNumDefs(),
@@ -343,33 +335,40 @@ void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) {
       int rx = RegIndex(mo.getReg());
       if (rx < 0) continue;
       if (DomainValue *dv = LiveRegs[rx]) {
+        // Bitmask of domains that dv and available have in common.
+        unsigned common = dv->getCommonDomains(available);
         // Is it possible to use this collapsed register for free?
-        if (dv->collapsed()) {
-          if (unsigned m = collmask & dv->Mask)
-            collmask = m;
-        } else if (dv->compat(collmask))
+        if (dv->isCollapsed()) {
+          // Restrict available domains to the ones in common with the operand.
+          // If there are no common domains, we must pay the cross-domain 
+          // penalty for this operand.
+          if (common) available = common;
+        } else if (common)
+          // Open DomainValue is compatible, save it for merging.
           used.push_back(rx);
         else
+          // Open DomainValue is not compatible with instruction. It is useless
+          // now.
           Kill(rx);
       }
     }
 
   // If the collapsed operands force a single domain, propagate the collapse.
-  if (isPowerOf2_32(collmask)) {
-    unsigned domain = CountTrailingZeros_32(collmask);
+  if (isPowerOf2_32(available)) {
+    unsigned domain = CountTrailingZeros_32(available);
     TII->SetSSEDomain(mi, domain);
     visitHardInstr(mi, domain);
     return;
   }
 
-  // Kill off any remaining uses that don't match collmask, and build a list of
-  // incoming DomainValue that we want to merge.
+  // Kill off any remaining uses that don't match available, and build a list of
+  // incoming DomainValues that we want to merge.
   SmallVector<DomainValue*,4> doms;
   for (SmallVector<int, 4>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
     int rx = *i;
     DomainValue *dv = LiveRegs[rx];
     // This useless DomainValue could have been missed above.
-    if (!dv->compat(collmask)) {
+    if (!dv->getCommonDomains(available)) {
       Kill(*i);
       continue;
     }
@@ -388,28 +387,29 @@ void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) {
       doms.push_back(dv);
   }
 
-  //  doms are now sorted in order of appearance. Try to merge them all, giving
-  //  priority to the latest ones.
+  // doms are now sorted in order of appearance. Try to merge them all, giving
+  // priority to the latest ones.
   DomainValue *dv = 0;
   while (!doms.empty()) {
     if (!dv) {
       dv = doms.pop_back_val();
       continue;
     }
-    
-    DomainValue *ThisDV = doms.pop_back_val();
-    if (Merge(dv, ThisDV)) continue;
-    
+
+    DomainValue *latest = doms.pop_back_val();
+    if (Merge(dv, latest)) continue;
+
+    // If latest didn't merge, it is useless now. Kill all registers using it.
     for (SmallVector<int,4>::iterator i=used.begin(), e=used.end(); i != e; ++i)
-      if (LiveRegs[*i] == ThisDV)
+      if (LiveRegs[*i] == latest)
         Kill(*i);
   }
 
   // dv is the DomainValue we are going to use for this instruction.
   if (!dv)
-    dv = Pool.Alloc();
+    dv = Alloc();
   dv->Dist = Distance;
-  dv->Mask = collmask;
+  dv->AvailableDomains = available;
   dv->Instrs.push_back(mi);
 
   // Finally set all defs and non-collapsed uses to dv.
@@ -487,9 +487,10 @@ bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) {
   // DomainValues?
   for (LiveOutMap::const_iterator i = LiveOuts.begin(), e = LiveOuts.end();
          i != e; ++i)
-    free(i->second);
+    delete[] i->second;
   LiveOuts.clear();
-  Pool.Clear();
+  Avail.clear();
+  Allocator.DestroyAll();
 
   return false;
 }
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index 89cc84f..ec86fc2 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -164,33 +164,7 @@ include "X86RegisterInfo.td"
 
 include "X86InstrInfo.td"
 
-def X86InstrInfo : InstrInfo {
-
-  // Define how we want to layout our TargetSpecific information field... This
-  // should be kept up-to-date with the fields in the X86InstrInfo.h file.
-  let TSFlagsFields = ["FormBits",
-                       "hasOpSizePrefix",
-                       "hasAdSizePrefix",
-                       "Prefix",
-                       "hasREX_WPrefix",
-                       "ImmT.Value",
-                       "FPForm.Value",
-                       "hasLockPrefix",
-                       "SegOvrBits",
-                       "ExeDomain.Value",
-                       "Opcode"];
-  let TSFlagsShifts = [0,
-                       6,
-                       7,
-                       8,
-                       12,
-                       13,
-                       16,
-                       19,
-                       20,
-                       22,
-                       24];
-}
+def X86InstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // Calling Conventions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index c69eeb3..7849b51 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -54,8 +54,6 @@ class X86FastISel : public FastISel {
 
 public:
   explicit X86FastISel(MachineFunction &mf,
-                       MachineModuleInfo *mmi,
-                       DwarfWriter *dw,
                        DenseMap<const Value *, unsigned> &vm,
                        DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
                        DenseMap<const AllocaInst *, int> &am
@@ -63,7 +61,7 @@ public:
                        , SmallSet<Instruction*, 8> &cil
 #endif
                        )
-    : FastISel(mf, mmi, dw, vm, bm, am
+    : FastISel(mf, vm, bm, am
 #ifndef NDEBUG
                , cil
 #endif
@@ -1753,8 +1751,6 @@ unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
 
 namespace llvm {
   llvm::FastISel *X86::createFastISel(MachineFunction &mf,
-                        MachineModuleInfo *mmi,
-                        DwarfWriter *dw,
                         DenseMap<const Value *, unsigned> &vm,
                         DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
                         DenseMap<const AllocaInst *, int> &am
@@ -1762,7 +1758,7 @@ namespace llvm {
                         , SmallSet<Instruction*, 8> &cil
 #endif
                         ) {
-    return new X86FastISel(mf, mmi, dw, vm, bm, am
+    return new X86FastISel(mf, vm, bm, am
 #ifndef NDEBUG
                            , cil
 #endif
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 527e19b..64702f1 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1434,7 +1434,8 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
                           DebugLoc dl) {
   SDValue SizeNode     = DAG.getConstant(Flags.getByValSize(), MVT::i32);
   return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
-                       /*AlwaysInline=*/true, NULL, 0, NULL, 0);
+                       /*isVolatile*/false, /*AlwaysInline=*/true,
+                       NULL, 0, NULL, 0);
 }
 
 /// IsTailCallConvention - Return true if the calling convention is one that
@@ -2397,8 +2398,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
 }
 
 FastISel *
-X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
-                            DwarfWriter *dw,
+X86TargetLowering::createFastISel(MachineFunction &mf,
                             DenseMap<const Value *, unsigned> &vm,
                             DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
                             DenseMap<const AllocaInst *, int> &am
@@ -2406,7 +2406,7 @@ X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
                           , SmallSet<Instruction*, 8> &cil
 #endif
                                   ) {
-  return X86::createFastISel(mf, mmo, dw, vm, bm, am
+  return X86::createFastISel(mf, vm, bm, am
 #ifndef NDEBUG
                              , cil
 #endif
@@ -6548,6 +6548,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
                                            SDValue Chain,
                                            SDValue Dst, SDValue Src,
                                            SDValue Size, unsigned Align,
+                                           bool isVolatile,
                                            const Value *DstSV,
                                            uint64_t DstSVOff) {
   ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -6676,7 +6677,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
                                       DAG.getConstant(Offset, AddrVT)),
                           Src,
                           DAG.getConstant(BytesLeft, SizeVT),
-                          Align, DstSV, DstSVOff + Offset);
+                          Align, isVolatile, DstSV, DstSVOff + Offset);
   }
 
   // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
@@ -6687,7 +6688,7 @@ SDValue
 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
                                       SDValue Chain, SDValue Dst, SDValue Src,
                                       SDValue Size, unsigned Align,
-                                      bool AlwaysInline,
+                                      bool isVolatile, bool AlwaysInline,
                                       const Value *DstSV, uint64_t DstSVOff,
                                       const Value *SrcSV, uint64_t SrcSVOff) {
   // This requires the copy size to be a constant, preferrably
@@ -6746,7 +6747,7 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
                                     DAG.getNode(ISD::ADD, dl, SrcVT, Src,
                                                 DAG.getConstant(Offset, SrcVT)),
                                     DAG.getConstant(BytesLeft, SizeVT),
-                                    Align, AlwaysInline,
+                                    Align, isVolatile, AlwaysInline,
                                     DstSV, DstSVOff + Offset,
                                     SrcSV, SrcSVOff + Offset));
   }
@@ -6829,8 +6830,8 @@ SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
   DebugLoc dl = Op.getDebugLoc();
 
   return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
-                       DAG.getIntPtrConstant(24), 8, false,
-                       DstSV, 0, SrcSV, 0);
+                       DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
+                       false, DstSV, 0, SrcSV, 0);
 }
 
 SDValue
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 2c2a5fb..1026480 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -575,7 +575,6 @@ namespace llvm {
     /// or null if the target does not support "fast" ISel.
     virtual FastISel *
     createFastISel(MachineFunction &mf,
-                   MachineModuleInfo *mmi, DwarfWriter *dw,
                    DenseMap<const Value *, unsigned> &,
                    DenseMap<const BasicBlock *, MachineBasicBlock *> &,
                    DenseMap<const AllocaInst *, int> &
@@ -741,12 +740,13 @@ namespace llvm {
                                     SDValue Chain,
                                     SDValue Dst, SDValue Src,
                                     SDValue Size, unsigned Align,
+                                    bool isVolatile,
                                     const Value *DstSV, uint64_t DstSVOff);
     SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
                                     SDValue Chain,
                                     SDValue Dst, SDValue Src,
                                     SDValue Size, unsigned Align,
-                                    bool AlwaysInline,
+                                    bool isVolatile, bool AlwaysInline,
                                     const Value *DstSV, uint64_t DstSVOff,
                                     const Value *SrcSV, uint64_t SrcSVOff);
     
@@ -756,7 +756,7 @@ namespace llvm {
     /// block, the number of args, and whether or not the second arg is
     /// in memory or not.
     MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
-				unsigned argNum, bool inMem) const;
+                                unsigned argNum, bool inMem) const;
 
     /// Utility function to emit atomic bitwise operations (and, or, xor).
     /// It takes the bitwise instruction to expand, the associated machine basic
@@ -815,7 +815,6 @@ namespace llvm {
 
   namespace X86 {
     FastISel *createFastISel(MachineFunction &mf,
-                           MachineModuleInfo *mmi, DwarfWriter *dw,
                            DenseMap<const Value *, unsigned> &,
                            DenseMap<const BasicBlock *, MachineBasicBlock *> &,
                            DenseMap<const AllocaInst *, int> &
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td
index cbe4c82..c4522f3 100644
--- a/lib/Target/X86/X86InstrFormats.td
+++ b/lib/Target/X86/X86InstrFormats.td
@@ -128,6 +128,19 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
   bit hasLockPrefix = 0;    // Does this inst have a 0xF0 prefix?
   bits<2> SegOvrBits = 0;   // Segment override prefix.
   Domain ExeDomain = d;
+
+  // TSFlags layout should be kept in sync with X86InstrInfo.h.
+  let TSFlags{5-0}   = FormBits;
+  let TSFlags{6}     = hasOpSizePrefix;
+  let TSFlags{7}     = hasAdSizePrefix;
+  let TSFlags{11-8}  = Prefix;
+  let TSFlags{12}    = hasREX_WPrefix;
+  let TSFlags{15-13} = ImmT.Value;
+  let TSFlags{18-16} = FPForm.Value;
+  let TSFlags{19}    = hasLockPrefix;
+  let TSFlags{21-20} = SegOvrBits;
+  let TSFlags{23-22} = ExeDomain.Value;
+  let TSFlags{31-24} = Opcode;
 }
 
 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
@@ -314,8 +327,7 @@ class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
 // AES Instruction Templates:
 //
 // AES8I
-// FIXME: Verify these, they appear to use the same encoding as the SSE4.2 T8
-// and TA encodings.
+// These use the same encoding as the SSE4.2 T8 and TA encodings.
 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag>pattern>
       : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index fcb9947..ccb7b05 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -2961,10 +2961,6 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
       Load1->getOperand(2) == Load2->getOperand(2)) {
     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
       return false;
-    SDValue Op2 = Load1->getOperand(2);
-    if (!isa<RegisterSDNode>(Op2) ||
-        cast<RegisterSDNode>(Op2)->getReg() != 0)
-      return 0;
 
     // Now let's examine the displacements.
     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 65b7ec0..940b439 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -2707,7 +2707,7 @@ let isCodeGenOnly = 1 in {
                    "add{b}\t{$src2, $dst|$dst, $src2}", []>;
   def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
                     "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
-  def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
+  def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
                     "add{l}\t{$src2, $dst|$dst, $src2}", []>;
 }
 
diff --git a/lib/Target/X86/X86MCAsmInfo.cpp b/lib/Target/X86/X86MCAsmInfo.cpp
index 1afabc9..d257ee3 100644
--- a/lib/Target/X86/X86MCAsmInfo.cpp
+++ b/lib/Target/X86/X86MCAsmInfo.cpp
@@ -84,7 +84,6 @@ X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
   HasLEB128 = true;  // Target asm supports leb128 directives (little-endian)
 
   // Debug Information
-  AbsoluteDebugSectionOffsets = true;
   SupportsDebugInformation = true;
 
   // Exceptions handling
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 3238cce..32f28a5 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -297,9 +297,7 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   bool ghcCall = false;
 
   if (MF) {
-    const MachineFrameInfo *MFI = MF->getFrameInfo();
-    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
-    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
+    callsEHReturn = MF->getMMI().callsEHReturn();
     const Function *F = MF->getFunction();
     ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
   }
@@ -348,12 +346,8 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 const TargetRegisterClass* const*
 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
   bool callsEHReturn = false;
-
-  if (MF) {
-    const MachineFrameInfo *MFI = MF->getFrameInfo();
-    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
-    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
-  }
+  if (MF)
+    callsEHReturn = MF->getMMI().callsEHReturn();
 
   static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
     &X86::GR32RegClass, &X86::GR32RegClass,
@@ -443,14 +437,14 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 /// or if frame pointer elimination is disabled.
 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
-  const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
+  const MachineModuleInfo &MMI = MF.getMMI();
 
   return (NoFramePointerElim ||
           needsStackRealignment(MF) ||
           MFI->hasVarSizedObjects() ||
           MFI->isFrameAddressTaken() ||
           MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
-          (MMI && MMI->callsUnwindInit()));
+          MMI.callsUnwindInit());
 }
 
 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
@@ -800,14 +794,13 @@ void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
                                                 MCSymbol *Label,
                                                 unsigned FramePtr) const {
   MachineFrameInfo *MFI = MF.getFrameInfo();
-  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
-  if (!MMI) return;
+  MachineModuleInfo &MMI = MF.getMMI();
 
   // Add callee saved registers to move list.
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
   if (CSI.empty()) return;
 
-  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
+  std::vector<MachineMove> &Moves = MMI.getFrameMoves();
   const TargetData *TD = MF.getTarget().getTargetData();
   bool HasFP = hasFP(MF);
 
@@ -874,9 +867,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
   MachineFrameInfo *MFI = MF.getFrameInfo();
   const Function *Fn = MF.getFunction();
   const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
-  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
+  MachineModuleInfo &MMI = MF.getMMI();
   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
-  bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
+  bool needsFrameMoves = MMI.hasDebugInfo() ||
                           !Fn->doesNotThrow() || UnwindTablesMandatory;
   uint64_t MaxAlign  = MFI->getMaxAlignment(); // Desired stack alignment.
   uint64_t StackSize = MFI->getStackSize();    // Number of bytes to allocate.
@@ -935,7 +928,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
   //        REG < 64                    => DW_CFA_offset + Reg
   //        ELSE                        => DW_CFA_offset_extended
 
-  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
+  std::vector<MachineMove> &Moves = MMI.getFrameMoves();
   const TargetData *TD = MF.getTarget().getTargetData();
   uint64_t NumBytes = 0;
   int stackGrowth = -TD->getPointerSize();
@@ -959,7 +952,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
 
     if (needsFrameMoves) {
       // Mark the place where EBP/RBP was saved.
-      MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
+      MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
       BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
 
       // Define the current CFA rule to use the provided offset.
@@ -987,7 +980,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
 
     if (needsFrameMoves) {
       // Mark effective beginning of when frame pointer becomes valid.
-      MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
+      MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
       BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
 
       // Define the current CFA to use the EBP/RBP register.
@@ -1027,7 +1020,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
 
     if (!HasFP && needsFrameMoves) {
       // Mark callee-saved push instruction.
-      MCSymbol *Label = MMI->getContext().CreateTempSymbol();
+      MCSymbol *Label = MMI.getContext().CreateTempSymbol();
       BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
 
       // Define the current CFA rule to use the provided offset.
@@ -1099,7 +1092,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   if ((NumBytes || PushedRegs) && needsFrameMoves) {
     // Mark end of stack pointer adjustment.
-    MCSymbol *Label = MMI->getContext().CreateTempSymbol();
+    MCSymbol *Label = MMI.getContext().CreateTempSymbol();
     BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
 
     if (!HasFP && NumBytes) {