diff options
author | rdivacky <rdivacky@FreeBSD.org> | 2009-10-14 17:57:32 +0000 |
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committer | rdivacky <rdivacky@FreeBSD.org> | 2009-10-14 17:57:32 +0000 |
commit | cd749a9c07f1de2fb8affde90537efa4bc3e7c54 (patch) | |
tree | b21f6de4e08b89bb7931806bab798fc2a5e3a686 /lib/Target/X86/X86RegisterInfo.td | |
parent | 72621d11de5b873f1695f391eb95f0b336c3d2d4 (diff) | |
download | FreeBSD-src-cd749a9c07f1de2fb8affde90537efa4bc3e7c54.zip FreeBSD-src-cd749a9c07f1de2fb8affde90537efa4bc3e7c54.tar.gz |
Update llvm to r84119.
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.td')
-rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 344 |
1 files changed, 168 insertions, 176 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 2e6f017..7bf074d 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -270,42 +270,27 @@ def : SubRegSet<1, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" // cannot be encoded. def GR8 : RegisterClass<"X86", [i8], 8, - [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL, + [AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> { let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate SPL or BPL. - static const unsigned X86_GR8_AO_64_fp[] = { - X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, - X86::R8B, X86::R9B, X86::R10B, X86::R11B, - X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B - }; - // If not, just don't allocate SPL. static const unsigned X86_GR8_AO_64[] = { X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL }; - // In 32-mode, none of the 8-bit registers aliases EBP or ESP. - static const unsigned X86_GR8_AO_32[] = { - X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH - }; GR8Class::iterator GR8Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); - if (!Subtarget.is64Bit()) - return X86_GR8_AO_32; - else if (RI->hasFP(MF)) - return X86_GR8_AO_64_fp; - else + if (Subtarget.is64Bit()) return X86_GR8_AO_64; + else + return begin(); } GR8Class::iterator @@ -313,17 +298,20 @@ def GR8 : RegisterClass<"X86", [i8], 8, const TargetMachine &TM = MF.getTarget(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); + // Does the function dedicate RBP / EBP to being a frame ptr? if (!Subtarget.is64Bit()) - return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned)); + // In 32-mode, none of the 8-bit registers aliases EBP or ESP. + return begin() + 8; else if (RI->hasFP(MF)) - return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned)); + // If so, don't allocate SPL or BPL. + return array_endof(X86_GR8_AO_64) - 1; else - return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned)); + // If not, just don't allocate SPL. + return array_endof(X86_GR8_AO_64); } }]; } - def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP, R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> { @@ -333,42 +321,20 @@ def GR16 : RegisterClass<"X86", [i16], 16, iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate SP or BP. - static const unsigned X86_GR16_AO_64_fp[] = { - X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, - X86::R8W, X86::R9W, X86::R10W, X86::R11W, - X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W - }; - static const unsigned X86_GR16_AO_32_fp[] = { - X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX - }; - // If not, just don't allocate SP. static const unsigned X86_GR16_AO_64[] = { X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP }; - static const unsigned X86_GR16_AO_32[] = { - X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP - }; GR16Class::iterator GR16Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); - if (Subtarget.is64Bit()) { - if (RI->hasFP(MF)) - return X86_GR16_AO_64_fp; - else - return X86_GR16_AO_64; - } else { - if (RI->hasFP(MF)) - return X86_GR16_AO_32_fp; - else - return X86_GR16_AO_32; - } + if (Subtarget.is64Bit()) + return X86_GR16_AO_64; + else + return begin(); } GR16Class::iterator @@ -377,21 +343,26 @@ def GR16 : RegisterClass<"X86", [i16], 16, const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { + // Does the function dedicate RBP to being a frame ptr? if (RI->hasFP(MF)) - return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned)); + // If so, don't allocate SP or BP. + return array_endof(X86_GR16_AO_64) - 1; else - return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned)); + // If not, just don't allocate SP. + return array_endof(X86_GR16_AO_64); } else { + // Does the function dedicate EBP to being a frame ptr? if (RI->hasFP(MF)) - return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned)); + // If so, don't allocate SP or BP. + return begin() + 6; else - return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned)); + // If not, just don't allocate SP. + return begin() + 7; } } }]; } - def GR32 : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> { @@ -401,42 +372,20 @@ def GR32 : RegisterClass<"X86", [i32], 32, iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate ESP or EBP. - static const unsigned X86_GR32_AO_64_fp[] = { - X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, - X86::R8D, X86::R9D, X86::R10D, X86::R11D, - X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D - }; - static const unsigned X86_GR32_AO_32_fp[] = { - X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX - }; - // If not, just don't allocate ESP. static const unsigned X86_GR32_AO_64[] = { X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP }; - static const unsigned X86_GR32_AO_32[] = { - X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP - }; GR32Class::iterator GR32Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); - if (Subtarget.is64Bit()) { - if (RI->hasFP(MF)) - return X86_GR32_AO_64_fp; - else - return X86_GR32_AO_64; - } else { - if (RI->hasFP(MF)) - return X86_GR32_AO_32_fp; - else - return X86_GR32_AO_32; - } + if (Subtarget.is64Bit()) + return X86_GR32_AO_64; + else + return begin(); } GR32Class::iterator @@ -445,21 +394,29 @@ def GR32 : RegisterClass<"X86", [i32], 32, const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { + // Does the function dedicate RBP to being a frame ptr? if (RI->hasFP(MF)) - return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned)); + // If so, don't allocate ESP or EBP. + return array_endof(X86_GR32_AO_64) - 1; else - return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned)); + // If not, just don't allocate ESP. + return array_endof(X86_GR32_AO_64); } else { + // Does the function dedicate EBP to being a frame ptr? if (RI->hasFP(MF)) - return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned)); + // If so, don't allocate ESP or EBP. + return begin() + 6; else - return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned)); + // If not, just don't allocate ESP. + return begin() + 7; } } }]; } - +// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since +// RIP isn't really a register and it can't be used anywhere except in an +// address, but it doesn't cause trouble. def GR64 : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, RBX, R14, R15, R12, R13, RBP, RSP, RIP]> { @@ -483,6 +440,11 @@ def GR64 : RegisterClass<"X86", [i64], 64, }]; } +// Segment registers for use by MOV instructions (and others) that have a +// segment register as one operand. Always contain a 16-bit segment +// descriptor. +def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> { +} // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" @@ -509,38 +471,25 @@ def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> { // On x86-64, GR64_NOREX, GR32_NOREX and GR16_NOREX are the classes // of registers which do not by themselves require a REX prefix. def GR8_NOREX : RegisterClass<"X86", [i8], 8, - [AL, CL, DL, BL, AH, CH, DH, BH, + [AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL]> { let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate SPL or BPL. - static const unsigned X86_GR8_NOREX_AO_64_fp[] = { - X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL - }; - // If not, just don't allocate SPL. static const unsigned X86_GR8_NOREX_AO_64[] = { X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL }; - // In 32-mode, none of the 8-bit registers aliases EBP or ESP. - static const unsigned X86_GR8_NOREX_AO_32[] = { - X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH - }; GR8_NOREXClass::iterator GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); - if (!Subtarget.is64Bit()) - return X86_GR8_NOREX_AO_32; - else if (RI->hasFP(MF)) - return X86_GR8_NOREX_AO_64_fp; - else + if (Subtarget.is64Bit()) return X86_GR8_NOREX_AO_64; + else + return begin(); } GR8_NOREXClass::iterator @@ -548,15 +497,16 @@ def GR8_NOREX : RegisterClass<"X86", [i8], 8, const TargetMachine &TM = MF.getTarget(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); + // Does the function dedicate RBP / EBP to being a frame ptr? if (!Subtarget.is64Bit()) - return X86_GR8_NOREX_AO_32 + - (sizeof(X86_GR8_NOREX_AO_32) / sizeof(unsigned)); + // In 32-mode, none of the 8-bit registers aliases EBP or ESP. + return begin() + 8; else if (RI->hasFP(MF)) - return X86_GR8_NOREX_AO_64_fp + - (sizeof(X86_GR8_NOREX_AO_64_fp) / sizeof(unsigned)); + // If so, don't allocate SPL or BPL. + return array_endof(X86_GR8_NOREX_AO_64) - 1; else - return X86_GR8_NOREX_AO_64 + - (sizeof(X86_GR8_NOREX_AO_64) / sizeof(unsigned)); + // If not, just don't allocate SPL. + return array_endof(X86_GR8_NOREX_AO_64); } }]; } @@ -564,38 +514,20 @@ def GR16_NOREX : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> { let SubRegClassList = [GR8_NOREX, GR8_NOREX]; let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate SP or BP. - static const unsigned X86_GR16_AO_fp[] = { - X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX - }; - // If not, just don't allocate SP. - static const unsigned X86_GR16_AO[] = { - X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP - }; - - GR16_NOREXClass::iterator - GR16_NOREXClass::allocation_order_begin(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) - return X86_GR16_AO_fp; - else - return X86_GR16_AO; - } - GR16_NOREXClass::iterator GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); + // Does the function dedicate RBP / EBP to being a frame ptr? if (RI->hasFP(MF)) - return X86_GR16_AO_fp+(sizeof(X86_GR16_AO_fp)/sizeof(unsigned)); + // If so, don't allocate SP or BP. + return end() - 2; else - return X86_GR16_AO + (sizeof(X86_GR16_AO) / sizeof(unsigned)); + // If not, just don't allocate SP. + return end() - 1; } }]; } @@ -604,89 +536,149 @@ def GR32_NOREX : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> { let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX]; let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate ESP or EBP. - static const unsigned X86_GR32_NOREX_AO_fp[] = { - X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX - }; - // If not, just don't allocate ESP. - static const unsigned X86_GR32_NOREX_AO[] = { - X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP - }; - GR32_NOREXClass::iterator - GR32_NOREXClass::allocation_order_begin(const MachineFunction &MF) const { + GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); + // Does the function dedicate RBP / EBP to being a frame ptr? if (RI->hasFP(MF)) - return X86_GR32_NOREX_AO_fp; + // If so, don't allocate ESP or EBP. + return end() - 2; else - return X86_GR32_NOREX_AO; + // If not, just don't allocate ESP. + return end() - 1; } - - GR32_NOREXClass::iterator - GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const { + }]; +} +// GR64_NOREX - GR64 registers which do not require a REX prefix. +def GR64_NOREX : RegisterClass<"X86", [i64], 64, + [RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> { + let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX]; + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + GR64_NOREXClass::iterator + GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); + // Does the function dedicate RBP to being a frame ptr? if (RI->hasFP(MF)) - return X86_GR32_NOREX_AO_fp + - (sizeof(X86_GR32_NOREX_AO_fp) / sizeof(unsigned)); + // If so, don't allocate RIP, RSP or RBP. + return end() - 3; else - return X86_GR32_NOREX_AO + - (sizeof(X86_GR32_NOREX_AO) / sizeof(unsigned)); + // If not, just don't allocate RIP or RSP. + return end() - 2; } }]; } -// GR64_NOREX - GR64 registers which do not require a REX prefix. -def GR64_NOREX : RegisterClass<"X86", [i64], 64, - [RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP]> { - let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX]; +// GR32_NOSP - GR32 registers except ESP. +def GR32_NOSP : RegisterClass<"X86", [i32], 32, + [EAX, ECX, EDX, ESI, EDI, EBX, EBP, + R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> { + let SubRegClassList = [GR8, GR8, GR16]; let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // Does the function dedicate RBP / EBP to being a frame ptr? - // If so, don't allocate RSP or RBP. - static const unsigned X86_GR64_NOREX_AO_fp[] = { - X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX - }; - // If not, just don't allocate RSP. - static const unsigned X86_GR64_NOREX_AO[] = { - X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP + static const unsigned X86_GR32_NOSP_AO_64[] = { + X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, + X86::R8D, X86::R9D, X86::R10D, X86::R11D, + X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP }; - GR64_NOREXClass::iterator - GR64_NOREXClass::allocation_order_begin(const MachineFunction &MF) const { + GR32_NOSPClass::iterator + GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); + if (Subtarget.is64Bit()) + return X86_GR32_NOSP_AO_64; + else + return begin(); + } + + GR32_NOSPClass::iterator + GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) - return X86_GR64_NOREX_AO_fp; + const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); + if (Subtarget.is64Bit()) { + // Does the function dedicate RBP to being a frame ptr? + if (RI->hasFP(MF)) + // If so, don't allocate EBP. + return array_endof(X86_GR32_NOSP_AO_64) - 1; + else + // If not, any reg in this class is ok. + return array_endof(X86_GR32_NOSP_AO_64); + } else { + // Does the function dedicate EBP to being a frame ptr? + if (RI->hasFP(MF)) + // If so, don't allocate EBP. + return begin() + 6; + else + // If not, any reg in this class is ok. + return begin() + 7; + } + } + }]; +} + +// GR64_NOSP - GR64 registers except RSP (and RIP). +def GR64_NOSP : RegisterClass<"X86", [i64], 64, + [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, + RBX, R14, R15, R12, R13, RBP]> { + let SubRegClassList = [GR8, GR8, GR16, GR32_NOSP]; + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + GR64_NOSPClass::iterator + GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); + const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); + if (!Subtarget.is64Bit()) + return begin(); // None of these are allocatable in 32-bit. + if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr? + return end()-1; // If so, don't allocate RBP else - return X86_GR64_NOREX_AO; + return end(); // If not, any reg in this class is ok. } + }]; +} - GR64_NOREXClass::iterator - GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const { +// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. +def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, + [RAX, RCX, RDX, RSI, RDI, RBX, RBP]> { + let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX]; + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + GR64_NOREX_NOSPClass::iterator + GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); + // Does the function dedicate RBP to being a frame ptr? if (RI->hasFP(MF)) - return X86_GR64_NOREX_AO_fp + - (sizeof(X86_GR64_NOREX_AO_fp) / sizeof(unsigned)); + // If so, don't allocate RBP. + return end() - 1; else - return X86_GR64_NOREX_AO + - (sizeof(X86_GR64_NOREX_AO) / sizeof(unsigned)); + // If not, any reg in this class is ok. + return end(); } }]; } // A class to support the 'A' assembler constraint: EAX then EDX. -def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]>; +def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> { + let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD]; +} // Scalar SSE2 floating point registers. def FR32 : RegisterClass<"X86", [f32], 32, |