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| author | rdivacky <rdivacky@FreeBSD.org> | 2009-11-04 14:58:56 +0000 |
|---|---|---|
| committer | rdivacky <rdivacky@FreeBSD.org> | 2009-11-04 14:58:56 +0000 |
| commit | 7ff99155c39edd73ebf1c6adfa023b1048fee9a4 (patch) | |
| tree | b4dc751bcee540346911aa4115729eff2f991657 /lib/Target/SystemZ/SystemZISelLowering.cpp | |
| parent | d1f06de484602e72707476a6152974847bac1570 (diff) | |
| download | FreeBSD-src-7ff99155c39edd73ebf1c6adfa023b1048fee9a4.zip FreeBSD-src-7ff99155c39edd73ebf1c6adfa023b1048fee9a4.tar.gz | |
Update LLVM to r86025.
Diffstat (limited to 'lib/Target/SystemZ/SystemZISelLowering.cpp')
| -rw-r--r-- | lib/Target/SystemZ/SystemZISelLowering.cpp | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 07e0d83..5c8cae0 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -53,11 +53,6 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : if (!UseSoftFloat) { addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); - - addLegalFPImmediate(APFloat(+0.0)); // lzer - addLegalFPImmediate(APFloat(+0.0f)); // lzdr - addLegalFPImmediate(APFloat(-0.0)); // lzer + lner - addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr } // Compute derived properties from the register classes @@ -80,7 +75,13 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); setStackPointerRegisterToSaveRestore(SystemZ::R15D); - setSchedulingPreference(SchedulingForLatency); + + // TODO: It may be better to default to latency-oriented scheduling, however + // LLVM's current latency-oriented scheduler can't handle physreg definitions + // such as SystemZ has with PSW, so set this to the register-pressure + // scheduler, because it can. + setSchedulingPreference(SchedulingForRegPressure); + setBooleanContents(ZeroOrOneBooleanContent); setOperationAction(ISD::BR_JT, MVT::Other, Expand); @@ -169,6 +170,17 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { } } +bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { + if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64)) + return false; + + // +0.0 lzer + // +0.0f lzdr + // -0.0 lzer + lner + // -0.0f lzdr + lndr + return Imm.isZero() || Imm.isNegZero(); +} + //===----------------------------------------------------------------------===// // SystemZ Inline Assembly Support //===----------------------------------------------------------------------===// @@ -657,7 +669,7 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, DebugLoc dl = LHS.getDebugLoc(); return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), - dl, MVT::Flag, LHS, RHS); + dl, MVT::i64, LHS, RHS); } |
